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Searched refs:MCIF_WB_NB_PSTATE_CONTROL (Results 1 - 3 of 3) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_mmhubbub.c	`184 REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x0); 188 REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x1); 192 REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x2); 196 REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x3);`
dcn20_mmhubbub.h	`96 SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\ 478 uint32_t MCIF_WB_NB_PSTATE_CONTROL;\`
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_dwb.h	`82 SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\ 245 uint32_t MCIF_WB_NB_PSTATE_CONTROL;`

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