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    Searched refs:MCR (Results 1 - 17 of 17) sorted by relevancy

  /src/sys/arch/evbsh3/stand/mesboot/src/
mesboot.c 69 switch(MCR) {
  /src/external/gpl3/gcc/dist/gcc/config/arm/
arm_acle_builtins.def 37 VAR1 (MCR, mcr, void)
38 VAR1 (MCR, mcr2, void)
  /src/external/gpl3/gcc.old/dist/gcc/config/arm/
arm_acle_builtins.def 37 VAR1 (MCR, mcr, void)
38 VAR1 (MCR, mcr2, void)
  /src/sys/arch/mmeye/mmeye/
machdep.c 576 #define MCR 4
620 OUTP(MCR, 0);
625 OUTP(MCR, RTS_MODE | MCR_OUT2);
  /src/sys/arch/hpc/conf/
platid.def 103 MCR " MC-R" {
  /src/crypto/external/bsd/openssl/dist/util/perl/OpenSSL/
Util.pm 198 # means running them with the MCR command. This is an old PDP-11
202 my $prefix = 'MCR';
204 if ($prog =~ /^MCR$/i) {
205 # If the first element is "MCR" (independent of case) already, then
211 # that there is one. Otherwise, MCR assumes that the program
  /src/external/gpl3/gdb/dist/sim/arm/
armsupp.c 1023 /* This function does the Busy-Waiting for an MCR instruction. */
1036 cpab = (state->MCR[CPNum]) (state, ARMul_FIRST, instr, source);
1044 cpab = (state->MCR[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
1048 cpab = (state->MCR[CPNum]) (state, ARMul_BUSY, instr, source);
armdefs.h 119 ARMul_MCRs *MCR[16]; /* MCR instruction */
399 ARMul_MRCs * mrc, ARMul_MCRs * mcr,
armcopro.c 994 2) You can only access its registers with MCR and MRC.
1109 Sixteen registers. Both co-processor nuimbers can be used in an MCR
1307 LDC routine, STC routine, MRC routine, MCR routine,
1393 ARMul_MCRs * mcr,
1408 if (mcr != NULL)
1409 state->MCR[number] = mcr;
  /src/external/gpl3/gdb.old/dist/sim/arm/
armsupp.c 1023 /* This function does the Busy-Waiting for an MCR instruction. */
1036 cpab = (state->MCR[CPNum]) (state, ARMul_FIRST, instr, source);
1044 cpab = (state->MCR[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
1048 cpab = (state->MCR[CPNum]) (state, ARMul_BUSY, instr, source);
armdefs.h 119 ARMul_MCRs *MCR[16]; /* MCR instruction */
399 ARMul_MRCs * mrc, ARMul_MCRs * mcr,
armcopro.c 994 2) You can only access its registers with MCR and MRC.
1109 Sixteen registers. Both co-processor nuimbers can be used in an MCR
1307 LDC routine, STC routine, MRC routine, MCR routine,
1393 ARMul_MCRs * mcr,
1408 if (mcr != NULL)
1409 state->MCR[number] = mcr;
  /src/sys/arch/hpc/stand/hpcboot/sh3/dev/
sh3_dev.cpp 176 DUMP_BSC_REG(MCR);
  /src/sys/arch/sandpoint/stand/altboot/
brdsetup.c 85 #define MCR 4
  /src/crypto/external/bsd/openssl/dist/Configurations/
descrip.mms.tmpl 1058 PIPE MCR $gen0$gen_args > \$@
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 5360 // in the ACLE) then need to lower to MCR node (32 bit) or
5365 Opcode = IsThumb2 ? ARM::t2MCR : ARM::MCR;
ARMISelLowering.cpp 4024 // Some ARMv6 cpus can support data barriers with an mcr instruction.
19276 // Some ARMv6 cpus can support data barriers with an mcr instruction.
19280 Function *MCR = Intrinsic::getDeclaration(M, Intrinsic::arm_mcr);
19284 return Builder.CreateCall(MCR, args);

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