HomeSort by: relevance | last modified time | path
    Searched refs:MCSchedClassDesc (Results 1 - 25 of 28) sorted by relevancy

1 2

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetSchedule.h 47 unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
59 /// Return the MCSchedClassDesc for this instruction.
60 const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
103 const MCSchedClassDesc *SC = nullptr) const;
106 const MCSchedClassDesc *SC = nullptr) const;
110 const MCSchedClassDesc *SC = nullptr) const;
134 ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const {
138 ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const {
MachineTraceMetrics.h 66 struct MCSchedClassDesc;
288 ArrayRef<const MCSchedClassDesc *> ExtraInstrs = None,
289 ArrayRef<const MCSchedClassDesc *> RemoveInstrs = None) const;
ScheduleDAGInstrs.h 44 struct MCSchedClassDesc;
265 const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
MachineScheduler.h 758 std::pair<unsigned, unsigned> getNextResourceCycle(const MCSchedClassDesc *SC,
788 unsigned countResource(const MCSchedClassDesc *SC, unsigned PIdx,
ScheduleDAG.h 39 struct MCSchedClassDesc;
253 const MCSchedClassDesc *SchedClass =
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetSchedule.cpp 86 const MCSchedClassDesc *SC) const {
97 const MCSchedClassDesc *SC) const {
108 const MCSchedClassDesc *SC) const {
130 /// Return the MCSchedClassDesc for this instruction. Some SchedClasses require
132 const MCSchedClassDesc *TargetSchedModel::
136 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
217 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
229 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
256 TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &SCDesc) const {
282 const MCSchedClassDesc *SCDesc = resolveSchedClass(MI)
    [all...]
MachineCombiner.cpp 117 SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC);
391 SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC) {
395 const MCSchedClassDesc *SC = SchedModel.getSchedClassDesc(Idx);
416 SmallVector<const MCSchedClassDesc *, 16> InsInstrsSC;
417 SmallVector<const MCSchedClassDesc *, 16> DelInstrsSC;
422 ArrayRef<const MCSchedClassDesc *> MSCInsArr = makeArrayRef(InsInstrsSC);
423 ArrayRef<const MCSchedClassDesc *> MSCDelArr = makeArrayRef(DelInstrsSC);
MachineTraceMetrics.cpp 122 const MCSchedClassDesc *SC = SchedModel.resolveSchedClass(&MI);
1226 ArrayRef<const MCSchedClassDesc *> ExtraInstrs,
1227 ArrayRef<const MCSchedClassDesc *> RemoveInstrs) const {
1234 auto extraCycles = [this](ArrayRef<const MCSchedClassDesc *> Instrs,
1238 for (const MCSchedClassDesc *SC : Instrs) {
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCSchedule.h 110 struct MCSchedClassDesc {
307 const MCSchedClassDesc *SchedClassTable;
347 const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const {
356 const MCSchedClassDesc &SCDesc);
362 // Returns the reciprocal throughput information from a MCSchedClassDesc.
365 const MCSchedClassDesc &SCDesc);
MCSubtargetInfo.h 167 const MCSchedClassDesc *SC) const {
171 const MCSchedClassDesc *SC) const {
175 const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
183 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
205 getReadAdvanceEntries(const MCSchedClassDesc &SC) const {
  /src/external/apache2/llvm/dist/llvm/lib/MC/
MCSchedule.cpp 41 const MCSchedClassDesc &SCDesc) {
58 const MCSchedClassDesc &SCDesc = *getSchedClassDesc(SchedClass);
71 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass);
89 const MCSchedClassDesc &SCDesc) {
114 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass);
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
SchedClassResolution.h 38 // An MCSchedClassDesc augmented with some additional data.
52 const MCSchedClassDesc *const SCDesc;
SchedClassResolution.cpp 50 getNonRedundantWriteProcRes(const MCSchedClassDesc &SCDesc,
Analysis.cpp 141 const MCSchedClassDesc *const SCDesc =
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZHazardRecognizer.cpp 47 const MCSchedClassDesc *SC = getSchedClass(SU);
93 const MCSchedClassDesc *SC = getSchedClass(SU);
171 const MCSchedClassDesc *SC = getSchedClass(SU);
272 const MCSchedClassDesc *SC = getSchedClass(SU);
341 const MCSchedClassDesc *SC = getSchedClass(SU);
390 const MCSchedClassDesc *SC = getSchedClass(SU);
418 const MCSchedClassDesc *SC = SchedModel->resolveSchedClass(MI);
SystemZHazardRecognizer.h 121 const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
SystemZMachineScheduler.cpp 255 const MCSchedClassDesc *SC = HazardRec->getSchedClass(SU);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64StorePairSuppress.cpp 86 const MCSchedClassDesc *SCDesc =
AArch64SIMDInstrOpt.cpp 229 const MCSchedClassDesc *SCDesc =
234 const MCSchedClassDesc *SCDescRepl;
  /src/external/apache2/llvm/dist/llvm/lib/MCA/
InstrBuilder.cpp 39 const MCSchedClassDesc &SCDesc,
207 const MCSchedClassDesc &SCDesc,
254 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID);
538 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID);
539 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) {
  /src/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/
InstructionInfoView.cpp 110 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID);
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
SubtargetEmitter.cpp 48 std::vector<std::vector<MCSchedClassDesc>> ProcSchedClasses;
985 std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back();
991 MCSchedClassDesc &SCDesc = SCTab.back();
1011 SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps;
1057 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
1090 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
1158 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
1179 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) {
1295 std::vector<MCSchedClassDesc> &SCTab =
1300 OS << "static const llvm::MCSchedClassDesc "
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
RegisterFile.cpp 480 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID);
560 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID);
  /src/external/apache2/llvm/dist/llvm/lib/MC/MCDisassembler/
Disassembler.cpp 210 const MCSchedClassDesc *SCDesc = SCModel.getSchedClassDesc(SCClass);
  /src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
InOrderIssueStage.cpp 102 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID);

Completed in 32 milliseconds

1 2