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    Searched refs:MEMCTL_BWSCON (Results 1 - 3 of 3) sorted by relevancy

/src/sys/arch/evbarm/stand/board/
smdk2410_ram_init.S	56 .word S3C2410_MEMCTL_BASE + MEMCTL_BWSCON /* address */
/src/sys/arch/evbarm/smdk2xx0/
smdk2410_machdep.c	427 ioreg_write32(S3C2410_MEMCTL_BASE + MEMCTL_BWSCON, 430 ioreg_read32(S3C2410_MEMCTL_BASE + MEMCTL_BWSCON));
/src/sys/arch/arm/s3c2xx0/
s3c24x0reg.h	44 #define MEMCTL_BWSCON 0x00 /* Bus width and wait status */

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Indexes created Mon Oct 27 04:09:48 GMT 2025