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    Searched refs:MESONGXBB_CLOCK_USB0_DDR_BRIDGE (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/arm/amlogic/
mesongxbb_clkc.h	96 #define MESONGXBB_CLOCK_USB0_DDR_BRIDGE 65
mesongxbb_clkc.c	222 MESON_CLK_GATE(MESONGXBB_CLOCK_USB0_DDR_BRIDGE, "usb0_ddr_bridge", "clk81", HHI_GCLK_MPEG2, 9),

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