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Searched refs:MESON_CLK_DIV_SET_RATE_PARENT (Results 1 - 6 of 6) sorted by relevancy

/src/sys/arch/arm/amlogic/
meson_clk_div.c	`96 if ((div->flags & MESON_CLK_DIV_SET_RATE_PARENT) != 0)`
meson8b_clkc.c	`197 MESON_CLK_DIV_POWER_OF_TWO \| MESON_CLK_DIV_SET_RATE_PARENT), 210 MESON_CLK_DIV_CPU_SCALE_TABLE \| MESON_CLK_DIV_SET_RATE_PARENT),`
meson_clk_pll.c	`115 if ((pll->flags & MESON_CLK_DIV_SET_RATE_PARENT) != 0)`
mesong12_clkc.c	`217 MESON_CLK_DIV_POWER_OF_TWO \| MESON_CLK_DIV_SET_RATE_PARENT) 235 MESON_CLK_DIV_POWER_OF_TWO \| MESON_CLK_DIV_SET_RATE_PARENT) 422 MESON_CLK_DIV_SET_RATE_PARENT) 970 MESON_CLK_DIV_SET_RATE_PARENT)`
mesongxbb_clkc.c	`107 MESON_CLK_DIV_POWER_OF_TWO \| MESON_CLK_DIV_SET_RATE_PARENT),`
meson_clk.h	`131 #define MESON_CLK_DIV_SET_RATE_PARENT __BIT(1)`

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