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    Searched refs:MESON_CLK_GATE (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/arch/arm/amlogic/
mesong12_aoclkc.c 70 MESON_CLK_GATE(MESONG12_CLOCK_AO_AHB, "ahb_ao",
72 MESON_CLK_GATE(MESONG12_CLOCK_AO_IR_IN,"ir_in_ao",
74 MESON_CLK_GATE(MESONG12_CLOCK_AO_I2C_M0, "i2c_m0_ao",
76 MESON_CLK_GATE(MESONG12_CLOCK_AO_I2C_S0, "i2c_s0_ao",
78 MESON_CLK_GATE(MESONG12_CLOCK_AO_UART, "uart_ao",
80 MESON_CLK_GATE(MESONG12_CLOCK_AO_PROD_I2C, "prod_i2c_ao",
82 MESON_CLK_GATE(MESONG12_CLOCK_AO_UART2, "uart2_ao",
84 MESON_CLK_GATE(MESONG12_CLOCK_AO_IR_OUT, "ir_out_ao",
86 MESON_CLK_GATE(MESONG12_CLOCK_AO_SAR_ADC, "sar_adc_ao",
88 MESON_CLK_GATE(MESONG12_CLOCK_AO_MAILBOX, "mailbox_ao"
    [all...]
mesongxbb_clkc.c 147 MESON_CLK_GATE(MESONGXBB_CLOCK_MPLL0, "mpll0", "mpll0_div", HHI_MPLL_CNTL7, 14),
148 MESON_CLK_GATE(MESONGXBB_CLOCK_MPLL1, "mpll1", "mpll1_div", HHI_MPLL_CNTL8, 14),
149 MESON_CLK_GATE(MESONGXBB_CLOCK_MPLL2, "mpll2", "mpll2_div", HHI_MPLL_CNTL9, 14),
157 MESON_CLK_GATE(MESONGXBB_CLOCK_FCLK_DIV2, "fclk_div2", "fclk_div2_div", HHI_MPLL_CNTL6, 27),
158 MESON_CLK_GATE(MESONGXBB_CLOCK_FCLK_DIV3, "fclk_div3", "fclk_div3_div", HHI_MPLL_CNTL6, 28),
159 MESON_CLK_GATE(MESONGXBB_CLOCK_FCLK_DIV4, "fclk_div4", "fclk_div4_div", HHI_MPLL_CNTL6, 29),
160 MESON_CLK_GATE(MESONGXBB_CLOCK_FCLK_DIV5, "fclk_div5", "fclk_div5_div", HHI_MPLL_CNTL6, 30),
161 MESON_CLK_GATE(MESONGXBB_CLOCK_FCLK_DIV7, "fclk_div7", "fclk_div7_div", HHI_MPLL_CNTL6, 31),
198 MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_A_CLK0, "sd_emmc_a_clk0", "sd_emmc_a_clk0_div", HHI_SD_EMMC_CLK_CNTL, 7),
199 MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_B_CLK0, "sd_emmc_b_clk0", "sd_emmc_b_clk0_div", HHI_SD_EMMC_CLK_CNTL, 23)
    [all...]
mesong12_clkc.c 244 MESON_CLK_GATE(MESONG12_CLOCK_FCLK_DIV2, "fclk_div2", \
261 MESON_CLK_GATE(MESONG12_CLOCK_FCLK_DIV3, "fclk_div3", \
271 MESON_CLK_GATE(MESONG12_CLOCK_FCLK_DIV4, "fclk_div4", \
281 MESON_CLK_GATE(MESONG12_CLOCK_FCLK_DIV5, "fclk_div5", \
291 MESON_CLK_GATE(MESONG12_CLOCK_FCLK_DIV7, "fclk_div7", \
327 MESON_CLK_GATE(MESONG12_CLOCK_MPLL0, "mpll0", \
332 MESON_CLK_GATE(MESONG12_CLOCK_MPLL1, "mpll1", \
337 MESON_CLK_GATE(MESONG12_CLOCK_MPLL2, "mpll2", \
394 MESON_CLK_GATE(MESONG12_CLOCK_SD_EMMC_A_CLK0, "sd_emmc_a_clk0", \
399 MESON_CLK_GATE(MESONG12_CLOCK_SD_EMMC_B_CLK0, "sd_emmc_b_clk0",
    [all...]
meson8b_clkc.c 277 MESON_CLK_GATE(MESON8B_CLOCK_MPLL0, "mpll0", "mpll0_div", HHI_MPLL_CNTL7, 14),
278 MESON_CLK_GATE(MESON8B_CLOCK_MPLL1, "mpll1", "mpll1_div", HHI_MPLL_CNTL8, 14),
279 MESON_CLK_GATE(MESON8B_CLOCK_MPLL2, "mpll2", "mpll2_div", HHI_MPLL_CNTL9, 14),
287 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV2, "fclk_div2", "fclk_div2_div", HHI_MPLL_CNTL6, 27),
288 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV3, "fclk_div3", "fclk_div3_div", HHI_MPLL_CNTL6, 28),
289 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV4, "fclk_div4", "fclk_div4_div", HHI_MPLL_CNTL6, 29),
290 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV5, "fclk_div5", "fclk_div5_div", HHI_MPLL_CNTL6, 30),
291 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV7, "fclk_div7", "fclk_div7_div", HHI_MPLL_CNTL6, 31),
303 MESON_CLK_GATE(MESON8B_CLOCK_CLK81, "clk81", "mpeg_div", HHI_MPEG_CLK_CNTL, 7),
305 MESON_CLK_GATE(MESON8B_CLOCK_I2C, "i2c", "clk81", HHI_GCLK_MPEG0, 9)
    [all...]
mesongxbb_aoclkc.c 69 MESON_CLK_GATE(MESONGXBB_CLOCK_AO_REMOTE, "remote_ao", GATE_PARENT, AO_RTI_GEN_CTNL_REG0, 0),
70 MESON_CLK_GATE(MESONGXBB_CLOCK_AO_I2C_MASTER, "i2c_master_ao", GATE_PARENT, AO_RTI_GEN_CTNL_REG0, 1),
71 MESON_CLK_GATE(MESONGXBB_CLOCK_AO_I2C_SLAVE, "i2c_slave_ao", GATE_PARENT, AO_RTI_GEN_CTNL_REG0, 2),
72 MESON_CLK_GATE(MESONGXBB_CLOCK_AO_UART1, "uart1_ao", GATE_PARENT, AO_RTI_GEN_CTNL_REG0, 3),
73 MESON_CLK_GATE(MESONGXBB_CLOCK_AO_UART2, "uart2_ao", GATE_PARENT, AO_RTI_GEN_CTNL_REG0, 5),
74 MESON_CLK_GATE(MESONGXBB_CLOCK_AO_IR_BLASTER, "ir_blaster_ao", GATE_PARENT, AO_RTI_GEN_CTNL_REG0, 6),
meson_clk_gate.c 1 /* $NetBSD: meson_clk_gate.c,v 1.2 2019/02/25 19:30:17 jmcneill Exp $ */
30 __KERNEL_RCSID(0, "$NetBSD: meson_clk_gate.c,v 1.2 2019/02/25 19:30:17 jmcneill Exp $");
43 struct meson_clk_gate *gate = &clk->u.gate;
47 KASSERT(clk->type == MESON_CLK_GATE);
68 struct meson_clk_gate *gate = &clk->u.gate;
70 KASSERT(clk->type == MESON_CLK_GATE);
meson_clk.h 61 MESON_CLK_GATE,
92 struct meson_clk_gate { struct
107 .type = MESON_CLK_GATE, \
118 #define MESON_CLK_GATE(_id, _name, _pname, _reg, _bit) \
337 struct meson_clk_gate gate;
meson_clk.c 345 case MESON_CLK_GATE: type = "gate"; break;

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