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    Searched refs:MG_PLL_DIV0 (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dpll_mgr.c 2864 pll_state->mg_pll_div0 = DKL_PLL_DIV0_INTEG_COEFF(int_coeff) |
2885 pll_state->mg_pll_div0 =
3170 hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port));
3238 hw_state->mg_pll_div0 = I915_READ(DKL_PLL_DIV0(tc_port));
3239 hw_state->mg_pll_div0 &= (DKL_PLL_DIV0_INTEG_COEFF_MASK |
3384 I915_WRITE(MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
3440 val |= hw_state->mg_pll_div0;
3654 "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x,
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  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_reg.h 10111 #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \

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