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    Searched refs:MG_PLL_DIV1 (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dpll_mgr.c 2869 pll_state->mg_pll_div1 = DKL_PLL_DIV1_IREF_TRIM(iref_trim) |
2890 pll_state->mg_pll_div1 =
3171 hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(tc_port));
3244 hw_state->mg_pll_div1 = I915_READ(DKL_PLL_DIV1(tc_port));
3245 hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK |
3385 I915_WRITE(MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
3446 val |= hw_state->mg_pll_div1;
3663 hw_state->mg_pll_div1,
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  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_reg.h 10126 #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \

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