| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCInstrBuilder.h | 32 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
35 return MIB.addImm(Offset).addFrameIndex(FI);
37 return MIB.addFrameIndex(FI).addImm(Offset);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEInstrBuilder.h | 32 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
35 return MIB.addFrameIndex(FI).addImm(0).addImm(Offset);
36 return MIB.addFrameIndex(FI).addImm(Offset);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| MVETailPredUtils.h | 92 MachineInstrBuilder MIB =
94 MIB.add(MI->getOperand(1));
95 MIB.addImm(0);
96 MIB.addImm(ARMCC::AL);
97 MIB.addReg(ARM::NoRegister);
99 MachineInstrBuilder MIB =
101 MIB.add(MI->getOperand(0));
102 MIB.add(MI->getOperand(1));
103 MIB.addImm(0);
104 MIB.addImm(ARMCC::AL)
[all...] |
| ARMInstructionSelector.cpp | 47 bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
231 static bool selectMergeValues(MachineInstrBuilder &MIB,
240 Register VReg0 = MIB.getReg(0);
245 Register VReg1 = MIB.getReg(1);
250 Register VReg2 = MIB.getReg(2);
256 MIB->setDesc(TII.get(ARM::VMOVDRR));
257 MIB.add(predOps(ARMCC::AL))
[all...] |
| Thumb2SizeReduction.cpp | 480 auto MIB = BuildMI(MBB, MI, dl, TII->get(Entry.NarrowOpc1))
488 MIB.setMemRefs(MI->memoperands());
491 MIB.setMIFlags(MI->getFlags());
592 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc));
597 MIB.addReg(MI->getOperand(0).getReg(), RegState::Define | RegState::Dead);
600 MIB.add(MI->getOperand(0));
601 MIB.add(MI->getOperand(1));
604 MIB.addImm(OffsetImm / Scale);
609 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) |
615 MIB.add(MI->getOperand(OpNum))
[all...] |
| ARMCallLowering.cpp | 90 MachineRegisterInfo &MRI, MachineInstrBuilder &MIB)
91 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
121 MIB.addUse(PhysReg, RegState::Implicit);
171 MachineInstrBuilder MIB;
423 MachineInstrBuilder MIB)
424 : ARMIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
427 MIB.addDef(PhysReg, RegState::Implicit);
430 MachineInstrBuilder MIB;
[all...] |
| ThumbRegisterInfo.cpp | 171 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
173 MIB = MIB.add(t1CondCodeOp());
175 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
177 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
178 MIB.add(predOps(ARMCC::AL));
311 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg);
313 MIB = MIB.add(t1CondCodeOp());
314 MIB.addReg(BaseReg, RegState::Kill)
[all...] |
| ARMExpandPseudoInsts.cpp | 537 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
556 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));
560 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
562 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
564 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
566 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
570 MIB.add(MI.getOperand(OpIdx++));
573 MIB.add(MI.getOperand(OpIdx++));
574 MIB.add(MI.getOperand(OpIdx++));
598 MIB.add(AM6Offset)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kInstrBuilder.h | 41 addOffset(const MachineInstrBuilder &MIB, int Offset) {
42 return MIB.addImm(Offset);
49 addRegIndirectWithDisp(const MachineInstrBuilder &MIB, Register Reg,
51 return MIB.addImm(Offset).addReg(Reg, getKillRegState(IsKill));
59 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
60 MachineInstr *MI = MIB;
72 return MIB.addImm(Offset).addFrameIndex(FI).addMemOperand(MMO);
76 addMemOperand(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
77 MachineInstr *MI = MIB;
89 return MIB.addMemOperand(MMO)
[all...] |
| M68kExpandPseudo.cpp | 76 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
85 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8);
87 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8);
89 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16);
92 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8);
94 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i8);
96 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i16);
99 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i16, MVT::i8);
101 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i8);
103 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i16)
[all...] |
| M68kInstrInfo.cpp | 348 bool M68kInstrInfo::ExpandMOVX_RR(MachineInstrBuilder &MIB, MVT MVTDst,
351 unsigned Dst = MIB->getOperand(0).getReg();
352 unsigned Src = MIB->getOperand(1).getReg();
368 DebugLoc DL = MIB->getDebugLoc();
373 LLVM_DEBUG(dbgs() << "Remove " << *MIB.getInstr() << '\n');
374 MIB->eraseFromParent();
376 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to MOV\n");
377 MIB->setDesc(get(Move));
378 MIB->getOperand(1).setReg(SSrc);
386 bool M68kInstrInfo::ExpandMOVSZX_RR(MachineInstrBuilder &MIB, bool IsSigned
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 124 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
143 addOffset(const MachineInstrBuilder &MIB, int Offset) {
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
148 addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) {
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0);
157 addRegOffset(const MachineInstrBuilder &MIB,
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
164 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1
[all...] |
| X86CallLowering.cpp | 86 MachineRegisterInfo &MRI, MachineInstrBuilder &MIB)
87 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB),
109 MIB.addUse(PhysReg, RegState::Implicit);
126 MachineInstrBuilder &MIB;
138 auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
153 X86OutgoingValueHandler Handler(MIRBuilder, MRI, MIB);
160 MIRBuilder.insertInstr(MIB);
225 MachineInstrBuilder &MIB)
226 : X86IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {
[all...] |
| X86FixupBWInsts.cpp | 297 MachineInstrBuilder MIB =
302 MIB.add(MI->getOperand(i));
304 MIB.setMemRefs(MI->memoperands());
306 return MIB;
332 MachineInstrBuilder MIB =
340 MIB.add(Op);
342 return MIB;
360 MachineInstrBuilder MIB =
365 MIB.add(MI->getOperand(i));
367 MIB.setMemRefs(MI->memoperands())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZInstrBuilder.h | 23 /// Add a BDX memory reference for frame object FI to MIB.
25 addFrameReference(const MachineInstrBuilder &MIB, int FI) {
26 MachineInstr *MI = MIB;
39 return MIB.addFrameIndex(FI).addImm(Offset).addReg(0).addMemOperand(MMO);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| CSEMIRBuilder.cpp | 120 MachineInstrBuilder CSEMIRBuilder::memoizeMI(MachineInstrBuilder MIB,
122 assert(canPerformCSEForOpc(MIB->getOpcode()) &&
124 MachineInstr *MIBInstr = MIB;
126 return MIB;
141 MachineInstrBuilder &MIB) {
143 "Impossible return a single MIB with copies to multiple defs");
147 return buildCopy(Op.getReg(), MIB.getReg(0));
157 Observer->changingInstr(*MIB);
158 MIB->setDebugLoc(
159 DILocation::getMergedLocation(MIB->getDebugLoc(), getDebugLoc()))
[all...] |
| MachineIRBuilder.cpp | 41 MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
42 return MIB;
45 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
46 getMBB().insert(getInsertPt(), MIB);
47 recordInsertion(MIB);
48 return MIB;
100 auto MIB = buildInstrNoInsert(TargetOpcode::DBG_VALUE);
103 MIB.addCImm(CI);
105 MIB.addImm(CI->getZExtValue());
107 MIB.addFPImm(CFP)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 193 MachineInstrBuilder &MIB,
231 MIB.addReg(VRBase, RegState::Define);
244 MIB.addReg(VRBase, RegState::Define);
256 MIB.addReg(VRBase, RegState::Define);
299 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
311 const MCInstrDesc &MCID = MIB->getDesc();
353 unsigned Idx = MIB->getNumOperands();
355 MIB->getOperand(Idx-1).isReg() &&
356 MIB->getOperand(Idx-1).isImplicit())
363 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill)
[all...] |
| InstrEmitter.h | 53 MachineInstrBuilder &MIB,
66 void AddRegisterOperand(MachineInstrBuilder &MIB,
77 void AddOperand(MachineInstrBuilder &MIB,
112 void AddDbgValueLocationOps(MachineInstrBuilder &MIB,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUInstructionSelector.cpp | 522 MachineInstrBuilder MIB =
526 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef()));
527 MIB.addImm(SubRegs[I]);
668 auto MIB = BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), Dst)
673 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
820 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::V_WRITELANE_B32), VDst);
827 MIB.addReg(Val);
828 MIB.addImm(ConstSelect->Value.getSExtValue() &
838 MIB.addImm(ConstVal->Value.getSExtValue());
839 MIB.addReg(LaneSelect)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonOptAddrMode.cpp | 492 MachineInstrBuilder MIB;
498 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
499 MIB.add(OldMI->getOperand(0));
500 MIB.add(OldMI->getOperand(2));
501 MIB.add(OldMI->getOperand(3));
502 MIB.add(ImmOp);
509 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode))
514 MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags());
521 LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
526 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64InstructionSelector.cpp | 78 MIB.setMF(MF);
120 MachineIRBuilder &MIB) const;
122 MachineIRBuilder &MIB) const;
124 MachineIRBuilder &MIB) const;
127 MachineIRBuilder &MIB) const;
292 MachineIRBuilder &MIB) const;
297 MachineIRBuilder &MIB) const;
400 MachineIRBuilder &MIB) const;
404 void renderTruncImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
406 void renderLogicalImm32(MachineInstrBuilder &MIB, const MachineInstr &I
[all...] |
| AArch64PostLegalizerLowering.cpp | 505 MachineIRBuilder MIB(MI);
506 auto ImmDef = MIB.buildConstant(LLT::scalar(32), Imm);
507 MIB.buildInstr(NewOpc, {MI.getOperand(0)}, {MI.getOperand(1), ImmDef});
631 MachineIRBuilder &MIB, GISelChangeObserver &Observer) {
632 MIB.setInstrAndDebugLoc(MI);
634 MachineRegisterInfo &MRI = *MIB.getMRI();
635 auto Cst = MIB.buildConstant(MRI.cloneVirtualRegister(RHS.getReg()),
865 return [LHS, RHS, IsZero, DstTy](MachineIRBuilder &MIB) {
867 ? MIB.buildInstr(AArch64::G_FCMEQZ, {DstTy}, {LHS})
868 : MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS})
[all...] |
| AArch64CallLowering.cpp | 207 MachineInstrBuilder MIB)
208 : IncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {}
211 MIB.addDef(PhysReg, RegState::Implicit);
214 MachineInstrBuilder MIB;
221 MachineInstrBuilder MIB)
222 : CallReturnHandler(MIRBuilder, MRI, MIB) {}
229 MachineInstrBuilder MIB, bool IsTailCall = false,
231 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB), IsTailCall(IsTailCall)
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| CSEMIRBuilder.h | 78 MachineInstrBuilder memoizeMI(MachineInstrBuilder MIB, void *NodeInsertPos);
83 MachineInstrBuilder &MIB);
86 // check if we can generate copies. It's not possible to return a single MIB,
|
