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    Searched refs:MICROSECOND_TIME_BASE_DIV (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_hwseq.c 95 value = REG_READ(MICROSECOND_TIME_BASE_DIV);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_i2c_hw.h 98 SR(MICROSECOND_TIME_BASE_DIV)
138 I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh),\
243 uint32_t MICROSECOND_TIME_BASE_DIV;
dce_hwseq.h 223 SR(MICROSECOND_TIME_BASE_DIV), \
288 SR(MICROSECOND_TIME_BASE_DIV), \
402 uint32_t MICROSECOND_TIME_BASE_DIV;
amdgpu_dce_i2c_hw.c 275 REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hwseq.c 231 * set MICROSECOND_TIME_BASE_DIV
237 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);

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