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    Searched refs:MIOpc (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64CondBrTuning.cpp 149 unsigned MIOpc = MI.getOpcode();
182 switch (MIOpc) {
191 if ((MIOpc == AArch64::TBZW || MIOpc == AArch64::TBNZW) &&
238 switch (MIOpc) {
247 if ((MIOpc == AArch64::TBZX || MIOpc == AArch64::TBNZX) &&
AArch64InstrInfo.cpp 1759 unsigned MIOpc = MI.getOpcode();
1760 if (MIOpc == AArch64::CSINCWr) {
1764 } else if (MIOpc == AArch64::CSINCXr) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrInfo.h 590 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc,
X86InstrInfo.cpp 1246 unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
1290 switch (MIOpc) {
1404 unsigned MIOpc = MI.getOpcode();
1405 switch (MIOpc) {
1463 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1468 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
1490 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1516 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1523 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUCallLowering.cpp 252 static ISD::NodeType extOpcodeToISDExtOpcode(unsigned MIOpc) {
253 switch (MIOpc) {

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