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    Searched refs:MIPS3_TLB_ATTR_WB_NONCOHERENT (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/evbmips/ingenic/
cpu_startup.S	114 ori t0, t0, MIPS3_TLB_ATTR_WB_NONCOHERENT
/src/sys/arch/mips/include/
cpuregs.h	788 #define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */

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