| /src/sys/arch/mips/mips/ |
| cache_tx39_subr.S | 55 mfc0 t0, MIPS_COP_0_STATUS # Save SR.
57 mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts.
84 mtc0 t0, MIPS_COP_0_STATUS # Restore SR.
102 mfc0 t0, MIPS_COP_0_STATUS # Save SR.
104 mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts.
131 mtc0 t0, MIPS_COP_0_STATUS # Restore SR.
|
| cache_r3k_subr.S | 71 mfc0 v1, MIPS_COP_0_STATUS
73 mtc0 a0, MIPS_COP_0_STATUS # disable interrupts,
107 mtc0 v1, MIPS_COP_0_STATUS
150 mfc0 t0, MIPS_COP_0_STATUS # Save SR.
151 mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts.
161 mtc0 v1, MIPS_COP_0_STATUS
174 mtc0 t0, MIPS_COP_0_STATUS # Restore SR.
192 mfc0 t0, MIPS_COP_0_STATUS # Save SR.
193 mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts.
198 mtc0 v1, MIPS_COP_0_STATUS
[all...] |
| spl.S | 78 mfc0 v1, MIPS_COP_0_STATUS # fetch status register
86 mtc0 v1, MIPS_COP_0_STATUS # disable interrupts
88 mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
96 mtc0 a0, MIPS_COP_0_STATUS # store back
104 mfc0 v1, MIPS_COP_0_STATUS
136 mfc0 v1, MIPS_COP_0_STATUS # fetch status register
143 mtc0 v0, MIPS_COP_0_STATUS # disable interrupts
145 mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
149 mtc0 v1, MIPS_COP_0_STATUS # store back
161 mfc0 v1, MIPS_COP_0_STATUS
[all...] |
| mips_fpu.c | 116 "n"(MIPS_COP_0_STATUS));
206 __asm volatile ("mtc0 %0, $%1" :: "r"(status), "n"(MIPS_COP_0_STATUS));
246 : "r"(tf->tf_regs[_R_SR] & (MIPS_SR_COP_1_BIT|MIPS3_SR_FR|MIPS_SR_KX|MIPS_SR_INT_IE)), "n"(MIPS_COP_0_STATUS));
352 "n"(MIPS_COP_0_STATUS));
|
| locore_mips3.S | 176 mfc0 v0, MIPS_COP_0_STATUS
199 mfc0 v0, MIPS_COP_0_STATUS
591 mfc0 t0, MIPS_COP_0_STATUS # turn off interrupts
593 mtc0 t1, MIPS_COP_0_STATUS
607 mtc0 t0, MIPS_COP_0_STATUS # restore intr status.
620 mfc0 t0, MIPS_COP_0_STATUS # turn off interrupts
622 mtc0 t1, MIPS_COP_0_STATUS
637 mtc0 t0, MIPS_COP_0_STATUS # restore intr status.
656 mfc0 t0, MIPS_COP_0_STATUS
660 mtc0 t1, MIPS_COP_0_STATUS
[all...] |
| locore.S | 75 mfc0 k0, MIPS_COP_0_STATUS
79 mtc0 k0, MIPS_COP_0_STATUS
85 mtc0 k0, MIPS_COP_0_STATUS
91 mfc0 k0, MIPS_COP_0_STATUS
94 mtc0 k0, MIPS_COP_0_STATUS
96 mfc0 k0, MIPS_COP_0_STATUS
99 mtc0 k0, MIPS_COP_0_STATUS
159 mfc0 k0, MIPS_COP_0_STATUS
162 mtc0 k0, MIPS_COP_0_STATUS
169 mtc0 k0, MIPS_COP_0_STATUS
[all...] |
| mips_dsp.c | 131 [cp0_status] "n"(MIPS_COP_0_STATUS));
189 [cp0_status] "n"(MIPS_COP_0_STATUS));
|
| locore_mips1.S | 143 mfc0 k0, MIPS_COP_0_STATUS #00: get the status register
180 mfc0 k0, MIPS_COP_0_STATUS
238 mfc0 a0, MIPS_COP_0_STATUS # 1st arg is STATUS
309 mtc0 a0, MIPS_COP_0_STATUS # restore the SR, disable intrs
441 mfc0 s1, MIPS_COP_0_STATUS
509 mfc0 v1, MIPS_COP_0_STATUS
512 mtc0 v0, MIPS_COP_0_STATUS # write new status
526 mfc0 t0, MIPS_COP_0_STATUS # verify INT_IE is still set
566 mtc0 s1, MIPS_COP_0_STATUS # disable interrupts
588 mfc0 v0, MIPS_COP_0_STATUS
[all...] |
| mipsX_subr.S | 152 mtc0 zero, MIPS_COP_0_STATUS
154 li reg, MIPS_SR_EXL; mtc0 reg, MIPS_COP_0_STATUS
157 li reg, MIPS_SR_KX; mtc0 reg, MIPS_COP_0_STATUS
159 li reg, MIPS_SR_EXL | MIPS_SR_KX; mtc0 reg, MIPS_COP_0_STATUS
617 mfc0 k0, MIPS_COP_0_STATUS #00: get the status register
657 mfc0 k0, MIPS_COP_0_STATUS #00: get the status register
685 mfc0 k0, MIPS_COP_0_STATUS
741 mfc0 a0, MIPS_COP_0_STATUS # 1st arg is STATUS
817 mtc0 v0, MIPS_COP_0_STATUS # update.
841 mtc0 a0, MIPS_COP_0_STATUS # restore the SR, disable intr
[all...] |
| locore_octeon.S | 163 mfc0 k0, MIPS_COP_0_STATUS # get cp0 status
166 mtc0 k0, MIPS_COP_0_STATUS # write cp0 status
|
| db_disasm.c | 639 if (i.RType.rd == MIPS_COP_0_STATUS
|
| /src/sys/arch/hpcmips/vr/ |
| vrip_spl.S | 64 mfc0 v0, MIPS_COP_0_STATUS # fetch status register
69 mtc0 v0, MIPS_COP_0_STATUS # store back
|
| /src/sys/arch/mipsco/mipsco/ |
| locore_machdep.S | 45 mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts
47 mtc0 v0, MIPS_COP_0_STATUS # boot strap exception vector
|
| /src/sys/arch/newsmips/stand/boot/ |
| locore.S | 68 mfc0 v0, MIPS_COP_0_STATUS # save SR
69 mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
77 mtc0 v1, MIPS_COP_0_STATUS
85 mtc0 v0, MIPS_COP_0_STATUS # enable interrupts
|
| /src/sys/arch/sgimips/sgimips/ |
| ip22_cache.S | 49 mfc0 t0, MIPS_COP_0_STATUS ; \
56 mtc0 t1, MIPS_COP_0_STATUS ; \
63 mtc0 t0, MIPS_COP_0_STATUS ; \
|
| /src/sys/arch/mips/rmi/ |
| rmixl_spl.S | 86 mfc0 t0, MIPS_COP_0_STATUS # get STATUS
88 mtc0 zero, MIPS_COP_0_STATUS ## disable all ints in STATUS
94 mtc0 t0, MIPS_COP_0_STATUS ## set STATUS | IE
|
| rmixl_subr.S | 104 mfc0 t0, MIPS_COP_0_STATUS
119 mtc0 t0, MIPS_COP_0_STATUS
146 mtc0 t0, MIPS_COP_0_STATUS
|
| rmixl_fmnvar.h | 205 : "n"(MIPS_COP_0_STATUS), "n"(1 << 30));
226 : "n"(MIPS_COP_0_STATUS), "r"(mask), "r"(ocu));
|
| /src/sys/arch/evbmips/ingenic/ |
| clock.c | 120 printf("SR: %08x\n", MFC0(MIPS_COP_0_STATUS, 0));
126 printf("SR: %08x\n", MFC0(MIPS_COP_0_STATUS, 0));
131 printf("SR: %08x\n", MFC0(MIPS_COP_0_STATUS, 0));
|
| cpu_startup.S | 67 mtc0 v0, MIPS_COP_0_STATUS # reset to known state
|
| /src/sys/arch/pmax/pmax/ |
| locore_machdep.S | 148 mfc0 v0, MIPS_COP_0_STATUS # save original SR in v0
152 mtc0 v1, MIPS_COP_0_STATUS
160 mtc0 v0, MIPS_COP_0_STATUS # restore SR on exit
|
| /src/sys/arch/emips/stand/common/ |
| start.S | 151 mfc0 a0, MIPS_COP_0_STATUS
206 mtc0 k1, MIPS_COP_0_STATUS
317 mtc0 t0,MIPS_COP_0_STATUS
346 mfc0 v0, MIPS_COP_0_STATUS
355 mtc0 a0,MIPS_COP_0_STATUS
|
| /src/sys/arch/newsmips/newsmips/ |
| locore_machdep.S | 69 mtc0 v0, MIPS_COP_0_STATUS # boot strap exception vector
|
| /src/sys/arch/playstation2/playstation2/ |
| locore_machdep.S | 111 mtc0 t0, MIPS_COP_0_STATUS
|
| /src/sys/arch/mips/include/ |
| cpuregs.h | 517 * 12 MIPS_COP_0_STATUS 3333 Status register.
583 #define MIPS_COP_0_STATUS _(12)
|
