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  /src/sys/arch/hpcmips/vr/
vrip_spl.S 57 #define VR_INT_MASK_PIU MIPS_INT_MASK_0
vr.c 139 | MIPS_INT_MASK_0,
141 | MIPS_INT_MASK_0
554 if (ipending & MIPS_INT_MASK_0) {
  /src/sys/arch/evbmips/mipssim/
mipssim_intr.c 53 | MIPS_INT_MASK_0 | MIPS_INT_MASK_1
56 | MIPS_INT_MASK_0 | MIPS_INT_MASK_1
114 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0)
  /src/sys/arch/emips/include/
intr.h 50 #define MIPS_SPL0 (MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
  /src/sys/arch/pmax/include/
intr.h 45 #define MIPS_SPL0 (MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK)
  /src/sys/arch/algor/algor/
algor_intr.c 78 |MIPS_INT_MASK_0|MIPS_INT_MASK_1
141 if (pending & (MIPS_INT_MASK_0|MIPS_INT_MASK_1|MIPS_INT_MASK_2|
  /src/sys/arch/newsmips/newsmips/
news4000.c 62 | MIPS_INT_MASK_0
65 | MIPS_INT_MASK_0
127 if (ipending & MIPS_INT_MASK_0) {
news5000.c 67 | MIPS_INT_MASK_0
70 | MIPS_INT_MASK_0
173 if (ipending & MIPS_INT_MASK_0) {
news3400.c 71 | MIPS_INT_MASK_0
74 | MIPS_INT_MASK_0
131 if (ipending & MIPS_INT_MASK_0) {
  /src/sys/arch/cobalt/cobalt/
interrupt.c 144 [IPL_NONE] = MIPS_INT_MASK_0,
145 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0 | MIPS_INT_MASK_0,
146 [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0 | MIPS_INT_MASK_0,
147 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0,
148 [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0,
434 if (__predict_false(pending & MIPS_INT_MASK_0)) {
  /src/sys/arch/pmax/pmax/
interrupt.c 96 if (pending & (MIPS_INT_MASK_0|MIPS_INT_MASK_1|MIPS_INT_MASK_2|
dec_3min.c 244 mask = MIPS_INT_MASK_0;
414 if ((ipending & MIPS_INT_MASK_0) && intrtab[SYS_DEV_OPT0].ih_func) {
dec_3maxplus.c 130 [IPL_VM] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0,
384 if (ipending & MIPS_INT_MASK_0) {
  /src/sys/arch/mips/adm5120/
adm5120_intr.c 97 [IPL_VM] = MIPS_SOFT_INT_MASK|MIPS_INT_MASK_0,
271 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0)
  /src/sys/arch/mipsco/mipsco/
mips_3x30.c 64 #define MIPS_INT_MASK_SPL0 (MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1)
126 HANDLE_INTR(SYS_INTR_LEVEL0, MIPS_INT_MASK_0);
  /src/sys/arch/evbmips/ingenic/
intr.c 72 MIPS_INT_MASK_0 |
78 MIPS_INT_MASK_0 |
218 if (ipending & MIPS_INT_MASK_0) {
  /src/sys/arch/evbmips/malta/
malta_intr.c 73 [IPL_VM] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0,
74 [IPL_SCHED] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0
220 /* XXX - should check that MIPS_INT_MASK_0 is set... */
240 /* XXX - disable MIPS_INT_MASK_0 if list is empty? */
264 if (ipending & MIPS_INT_MASK_0) {
  /src/sys/arch/ews4800mips/ews4800mips/
tr2_intr.c 59 | MIPS_INT_MASK_0
63 | MIPS_INT_MASK_0
242 if (ipending & MIPS_INT_MASK_0) { /* FDD, PRINTER */
  /src/sys/arch/mips/atheros/
ar7100.c 78 MIPS_INT_MASK_0 | /* PCI */
81 MIPS_INT_MASK_0 | /* PCI */
86 MIPS_INT_MASK_0 | /* PCIE RC */
  /src/sys/arch/sgimips/sgimips/
machdep.c 135 [IPL_VM] = MIPS_INT_MASK_1|MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK,
137 MIPS_INT_MASK_1|MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK,
143 [IPL_VM] = MIPS_INT_MASK_2|MIPS_INT_MASK_1|MIPS_INT_MASK_0|
146 MIPS_INT_MASK_1|MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK,
155 [IPL_VM] = MIPS_INT_MASK_1|MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK,
162 [IPL_VM] = MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK,
163 [IPL_SCHED] = MIPS_INT_MASK_5|MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK,
cpu.c 147 if (pending & MIPS_INT_MASK_0) {
  /src/sys/arch/evbmips/sbmips/
sb1250_icu.c 66 [IPL_VM] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0
68 [IPL_SCHED] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0
70 [IPL_DDB] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0
  /src/sys/arch/sbmips/sbmips/
sb1250_icu.c 66 [IPL_VM] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0
68 [IPL_SCHED] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0
70 [IPL_DDB] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0
  /src/sys/arch/arc/arc/
c_magnum.c 95 | MIPS_INT_MASK_0
  /src/sys/arch/mips/cavium/
octeon_intr.c 83 [IPL_VM] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0,
84 [IPL_SCHED] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0
86 [IPL_DDB] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0
499 } else if (ipending & MIPS_INT_MASK_0) {

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