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  /src/sys/arch/arc/dti/
arcsisabr.c 120 (*platform->set_intr)(MIPS_INT_MASK_2, isabr_iointr, ARC_INTPRI_PCIISA);
tyneisabr.c 121 (*platform->set_intr)(MIPS_INT_MASK_2, isabr_iointr, ARC_INTPRI_PCIISA);
  /src/sys/arch/arc/jazz/
jazzisabr.c 121 (*platform->set_intr)(MIPS_INT_MASK_2, isabr_iointr, ARC_INTPRI_PCIISA);
  /src/sys/arch/emips/include/
intr.h 54 #define MIPS_SPL_0_1_2 (MIPS_INT_MASK_2|MIPS_SPL_0_1)
  /src/sys/arch/pmax/include/
intr.h 49 #define MIPS_SPL_0_1_2 (MIPS_INT_MASK_2|MIPS_SPL_0_1)
  /src/sys/arch/algor/algor/
algor_intr.c 79 |MIPS_INT_MASK_2|MIPS_INT_MASK_3,
141 if (pending & (MIPS_INT_MASK_0|MIPS_INT_MASK_1|MIPS_INT_MASK_2|
  /src/sys/arch/evbmips/mipssim/
mipssim_intr.c 54 | MIPS_INT_MASK_2,
57 | MIPS_INT_MASK_2 | MIPS_INT_MASK_5,
  /src/sys/arch/pmax/pmax/
interrupt.c 96 if (pending & (MIPS_INT_MASK_0|MIPS_INT_MASK_1|MIPS_INT_MASK_2|
dec_5100.c 100 mc_cpuspeed(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK), MIPS_INT_MASK_2);
171 if (ipending & MIPS_INT_MASK_2) {
dec_3min.c 250 mask = MIPS_INT_MASK_2;
423 if ((ipending & MIPS_INT_MASK_2) && intrtab[SYS_DEV_OPT2].ih_func) {
dec_3100.c 215 CALLINTR(SYS_DEV_SCC0, MIPS_INT_MASK_2);
  /src/sys/arch/mipsco/mipsco/
mips_3x30.c 66 #define MIPS_INT_MASK_SPL2 (MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1)
110 if (ipending & MIPS_INT_MASK_2) { /* Timer Interrupt */
  /src/sys/arch/newsmips/newsmips/
news4000.c 67 | MIPS_INT_MASK_2,
83 if (ipending & MIPS_INT_MASK_2) {
news5000.c 72 | MIPS_INT_MASK_2,
89 if (ipending & MIPS_INT_MASK_2) {
news3400.c 76 | MIPS_INT_MASK_2,
94 if (ipending & MIPS_INT_MASK_2) {
  /src/sys/arch/ews4800mips/ews4800mips/
tr2_intr.c 60 | MIPS_INT_MASK_2
64 | MIPS_INT_MASK_2
204 if (ipending & MIPS_INT_MASK_2) { /* ETHER, SCSI */
  /src/sys/arch/arc/arc/
c_magnum.c 97 | MIPS_INT_MASK_2
c_nec_eisa.c 119 | MIPS_INT_MASK_2,
c_nec_pci.c 124 | MIPS_INT_MASK_2,
  /src/sys/arch/sgimips/sgimips/
cpu.c 137 if (pending & MIPS_INT_MASK_2) {
  /src/sys/arch/evbmips/ingenic/
intr.c 80 MIPS_INT_MASK_2 |
212 if (ipending & MIPS_INT_MASK_2) {
  /src/sys/arch/mips/atheros/
ar7100.c 83 MIPS_INT_MASK_2 | /* GMAC0 */
88 MIPS_INT_MASK_2 | /* GMAC0 */
  /src/sys/arch/hpcmips/tx/
tx39icu.c 91 | MIPS_INT_MASK_2
94 | MIPS_INT_MASK_2
335 !(ipending & MIPS_INT_MASK_2)) {
350 if (ipending & MIPS_INT_MASK_2) {
  /src/sys/arch/evbmips/gdium/
gdium_intr.c 151 MIPS_INT_MASK_2 |
158 MIPS_INT_MASK_2 |
  /src/sys/arch/evbmips/loongson/
loongson_intr.c 81 MIPS_INT_MASK_2 |
88 MIPS_INT_MASK_2 |

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