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  /src/sys/arch/emips/include/
intr.h 52 #define MIPS_SPL3 (MIPS_INT_MASK_3|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
55 #define MIPS_SPL_0_1_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1)
56 #define MIPS_SPL_0_1_2_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1_2)
  /src/sys/arch/pmax/include/
intr.h 47 #define MIPS_SPL3 (MIPS_INT_MASK_3|MIPS_SOFT_INT_MASK)
50 #define MIPS_SPL_0_1_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1)
51 #define MIPS_SPL_0_1_2_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1_2)
  /src/sys/arch/arc/arc/
c_nec_jazz.c 59 MIPS_INT_MASK_3,
74 return MIPS_INT_MASK_3; /* Keep clock interrupts enabled */
118 out32(RD94_SYS_EXT_IMASK, cpu_int_mask & (~MIPS_INT_MASK_3 >> 10));
c_magnum.c 98 | MIPS_INT_MASK_3,
  /src/sys/arch/algor/algor/
algor_intr.c 79 |MIPS_INT_MASK_2|MIPS_INT_MASK_3,
142 MIPS_INT_MASK_3|MIPS_INT_MASK_4)) {
  /src/sys/arch/pmax/pmax/
interrupt.c 97 MIPS_INT_MASK_3|MIPS_INT_MASK_4)) {
dec_3100.c 138 mc_cpuspeed(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK), MIPS_INT_MASK_3);
201 if (ipending & MIPS_INT_MASK_3) {
dec_maxine.c 126 [IPL_VM] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_3,
356 if (ipending & MIPS_INT_MASK_3) {
dec_3min.c 155 /* enable posting of MIPS_INT_MASK_3 to CAUSE register */
158 mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_3);
328 if (ipending & MIPS_INT_MASK_3) {
dec_5100.c 194 if (ipending & MIPS_INT_MASK_3) {
202 * Handle write-to-nonexistent-address memory errors on MIPS_INT_MASK_3.
dec_3max.c 302 if (ipending & MIPS_INT_MASK_3) {
dec_3maxplus.c 387 if (ipending & MIPS_INT_MASK_3) {
  /src/sys/arch/mipsco/mipsco/
mips_3x30.c 57 #define INT_MASK_FPU MIPS_INT_MASK_3
67 #define MIPS_INT_MASK_SPL3 (MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2)
  /src/sys/arch/sgimips/sgimips/
cpu.c 132 if (pending & MIPS_INT_MASK_3) {
  /src/sys/arch/evbmips/ingenic/
intr.c 73 MIPS_INT_MASK_3 |
81 MIPS_INT_MASK_3 |
  /src/sys/arch/evbmips/malta/
malta_intr.c 252 if (ipending & (MIPS_INT_MASK_1 | MIPS_INT_MASK_3)) {
255 if (ipending & MIPS_INT_MASK_3)
  /src/sys/arch/mips/atheros/
ar7100.c 84 MIPS_INT_MASK_3, /* GMAC1 */
89 MIPS_INT_MASK_3 | /* GMAC1 */
ar5312.c 375 | MIPS_INT_MASK_3,
  /src/sys/arch/newsmips/newsmips/
news4000.c 117 if (ipending & MIPS_INT_MASK_3) {
news5000.c 159 if (ipending & MIPS_INT_MASK_3) {
news3400.c 59 #define INT_MASK_FPU MIPS_INT_MASK_3
  /src/sys/arch/evbmips/gdium/
gdium_intr.c 152 MIPS_INT_MASK_3 |
159 MIPS_INT_MASK_3 |
  /src/sys/arch/evbmips/loongson/
loongson_intr.c 82 MIPS_INT_MASK_3 |
89 MIPS_INT_MASK_3 |
  /src/sys/arch/ews4800mips/ews4800mips/
tr2_intr.c 191 if (ipending & MIPS_INT_MASK_3) { /* VME */
tr2a_intr.c 226 if ((ipending & MIPS_INT_MASK_3) && (intc_cause & INTC_INT3)) {

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