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  /src/sys/arch/evbmips/evbmips/
interrupt.c 81 if (pending & MIPS_INT_MASK_5) {
88 pending ^= MIPS_INT_MASK_5;
  /src/sys/arch/evbmips/sbmips/
sb1250_icu.c 61 [IPL_NONE] = MIPS_INT_MASK_5,
62 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0 | MIPS_INT_MASK_5,
63 [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0 | MIPS_INT_MASK_5,
64 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_5,
65 [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_5,
67 | MIPS_INT_MASK_5,
69 | MIPS_INT_MASK_1 | MIPS_INT_MASK_5,
72 | MIPS_INT_MASK_5,
305 if (pending & MIPS_INT_MASK_5) {
  /src/sys/arch/sbmips/sbmips/
sb1250_icu.c 61 [IPL_NONE] = MIPS_INT_MASK_5,
62 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0 | MIPS_INT_MASK_5,
63 [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0 | MIPS_INT_MASK_5,
64 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_5,
65 [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_5,
67 | MIPS_INT_MASK_5,
69 | MIPS_INT_MASK_1 | MIPS_INT_MASK_5,
72 | MIPS_INT_MASK_5,
305 if (pending & MIPS_INT_MASK_5) {
  /src/sys/arch/mips/rmi/
rmixl_spl.S 46 #define RMIXL_INT_MASK_5 (MIPS_INT_MASK_5 >> 8)
49 #define RMIXL_INT_MASK_5 (MIPS_INT_MASK_5 >> 8)
284 * - if clock intr is requested, set MIPS_INT_MASK_5
rmixl_intr.c 112 ((MIPS_INT_MASK_5|MIPS_SOFT_INT_MASK) >> 8)
451 const int vec = ffs(MIPS_INT_MASK_5 >> MIPS_INT_MASK_SHIFT) - 1;
903 eirr &= ~((MIPS_INT_MASK_5 | MIPS_SOFT_INT_MASK) >> 8);
  /src/sys/arch/emips/emips/
interrupt.c 121 if (ipending & MIPS_INT_MASK_5) {
130 if (ipending & MIPS_INT_MASK_5) {
xs_bee3.c 58 #define NOINTS (MIPS_INT_MASK_5|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
xilinx_ml40x.c 60 #define NOINTS (MIPS_INT_MASK_5|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
  /src/sys/arch/pmax/pmax/
interrupt.c 102 if (pending & MIPS_INT_MASK_5) {
  /src/sys/arch/mipsco/mipsco/
mips_3x30.c 69 #define MIPS_INT_MASK_SPL5 (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4)
121 if (ipending & MIPS_INT_MASK_5) /* level 5 interrupt */
  /src/sys/arch/algor/algor/
algor_intr.c 132 if (pending & MIPS_INT_MASK_5) {
  /src/sys/arch/arc/arc/
interrupt.c 111 if (ipending & MIPS_INT_MASK_5) {
  /src/sys/arch/ews4800mips/ews4800mips/
tr2_intr.c 66 | MIPS_INT_MASK_5,
154 if (ipending & MIPS_INT_MASK_5) { /* CLOCK */
226 (ipending & MIPS_INT_MASK_5)) {
tr2a_intr.c 56 [IPL_VM] = MIPS_INT_MASK & ~MIPS_INT_MASK_5,
183 if ((ipending & MIPS_INT_MASK_5) && (intc_cause & INTC_INT5)) {
  /src/sys/arch/evbmips/mipssim/
mipssim_intr.c 57 | MIPS_INT_MASK_2 | MIPS_INT_MASK_5,
  /src/sys/arch/sgimips/sgimips/
cpu.c 122 if (pending & MIPS_INT_MASK_5) {
  /src/sys/arch/evbmips/ingenic/
intr.c 75 MIPS_INT_MASK_5,
83 MIPS_INT_MASK_5,
  /src/sys/arch/newsmips/newsmips/
news4000.c 103 if (ipending & MIPS_INT_MASK_5) {
news5000.c 122 if (ipending & MIPS_INT_MASK_5) {
news3400.c 116 if (ipending & MIPS_INT_MASK_5) {
  /src/sys/arch/cobalt/cobalt/
interrupt.c 149 [IPL_VM] = MIPS_INT_MASK ^ MIPS_INT_MASK_5,
425 if (pending & MIPS_INT_MASK_5) {
  /src/sys/arch/mips/include/
cpuregs.h 323 #define MIPS_INT_MASK_5 0x8000
343 #define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
344 #define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
  /src/sys/arch/mips/cavium/
octeon_intr.c 85 | MIPS_INT_MASK_1 | MIPS_INT_MASK_5,
87 | MIPS_INT_MASK_1 | MIPS_INT_MASK_5,
  /src/sys/arch/evbmips/malta/
malta_intr.c 75 | MIPS_INT_MASK_5,
  /src/sys/arch/mips/ralink/
ralink_intr.c 61 [IPL_VM] = MIPS_INT_MASK ^ MIPS_INT_MASK_5,

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