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    Searched refs:MIPS_SR_INT_IE (Results 1 - 22 of 22) sorted by relevancy

  /src/sys/arch/mips/include/
psl.h 48 #define MIPS3_PSL_LOWIPL (MIPS3_INT_MASK | MIPS_SR_INT_IE)
59 MIPS_SR_INT_IE | \
69 #define MIPS1_PSL_LOWIPL (MIPS_INT_MASK | MIPS_SR_INT_IE)
cpuregs.h 206 * MIPS_SR_INT_IE Master (current) interrupt enable bit.
228 #define MIPS_SR_INT_IE 0x00000001
asm.h 800 ori sr, (MIPS_INT_MASK | MIPS_SR_INT_IE); \
  /src/sys/arch/evbmips/evbmips/
interrupt.c 61 KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
66 KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
68 KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
110 KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
  /src/sys/arch/mips/mips/
spl.S 84 or v1, MIPS_SR_INT_IE #
85 xor v1, MIPS_SR_INT_IE # clear interrupt enable bit
141 or v0, v1, MIPS_SR_INT_IE #
142 xor v0, MIPS_SR_INT_IE # clear interrupt enable bit
175 or v1, MIPS_SR_INT_IE # make sure interrupts are on
182 or v1, v0, MIPS_SR_INT_IE #
183 xor v1, MIPS_SR_INT_IE # clear interrupt enable bit
202 or v0, v1, MIPS_SR_INT_IE #
203 xor v0, MIPS_SR_INT_IE # clear interrupt enable bit
222 or v0, v1, MIPS_SR_INT_IE #
    [all...]
cache_r5k.c 232 mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE);
252 mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE);
302 mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE);
322 mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE);
358 mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE);
378 mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE);
440 mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE);
mips_fpu.c 115 : "r"(tf->tf_regs[_R_SR] & (MIPS_SR_COP_1_BIT|MIPS3_SR_FR|MIPS_SR_KX|MIPS_SR_INT_IE)),
246 : "r"(tf->tf_regs[_R_SR] & (MIPS_SR_COP_1_BIT|MIPS3_SR_FR|MIPS_SR_KX|MIPS_SR_INT_IE)), "n"(MIPS_COP_0_STATUS));
mips_softint.c 116 KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
locore.S 78 and k0, ~MIPS_SR_INT_IE
195 or v0, MIPS_SR_INT_IE
236 and t0, MIPS_SR_INT_IE
331 and t1, t0, MIPS_SR_INT_IE
334 and t1, t0, MIPS_SR_INT_IE
393 and v0, t1, MIPS_SR_INT_IE # assert interrupts are on
397 and v0, t1, MIPS_SR_INT_IE # assert interrupts are on
472 and v0, t1, MIPS_SR_INT_IE
528 and t0, v0, MIPS_SR_INT_IE
locore_mips3.S 177 andi v1, v0, MIPS_SR_INT_IE
200 andi v1, v0, MIPS_SR_INT_IE
592 and t1, t0, ~(MIPS_SR_INT_IE)
621 and t1, t0, ~(MIPS_SR_INT_IE)
658 and t2, t0, MIPS_SR_INT_IE # disable interrupts
locore_mips1.S 511 or v0, v1, MIPS_SR_INT_IE
528 and t0, MIPS_SR_INT_IE
590 or v0, MIPS_SR_INT_IE
794 or v0, MIPS_SR_INT_IE # make sure intrs are still on
796 li v0, MIPS_SR_INT_IE # reenable intrs
849 and v0, v1, MIPS_SR_INT_IE # clear interrupt enable
885 or t0, MIPS_SR_INT_IE # enable interrupts
964 li t0, MIPS_SR_INT_IE
968 ori t0, MIPS_SR_INT_IE # turn on IEc, enable intr.
vm_machdep.c 155 KASSERTMSG(pcb2->pcb_context.val[_L_SR] & MIPS_SR_INT_IE,
mipsX_subr.S 810 li v1, MIPS_SR_INT_IE << T_BREAK # make a mask of T_BREAK
813 and v1, MIPS_SR_INT_IE # restrict to IE bit
1196 and t0, MIPS_SR_INT_IE
1246 xor v0, MIPS_SR_INT_IE # disable interrupts
1276 or v0, MIPS_SR_INT_IE
1605 and v0, v1, MIPS_SR_INT_IE # clear interrupt enable
1644 or t0, MIPS_SR_INT_IE # enable interrupts
2559 and t0, v1, MIPS_SR_INT_IE
mips_machdep.c 2147 pcb->pcb_context.val[_L_SR] = MIPS_SR_INT_IE
2376 KASSERT((status & MIPS_SR_INT_IE) == 0);
cpu_subr.c 967 KASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
  /src/sys/arch/sgimips/sgimips/
ip22_cache.S 53 li v0, ~MIPS_SR_INT_IE /* ints off */ ; \
  /src/sys/arch/mips/rmi/
rmixl_spl.S 87 ori t0, MIPS_SR_INT_IE # set IE
  /src/sys/arch/evbmips/cavium/
autoconf.c 69 KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
  /src/sys/arch/mips/cavium/
octeon_intr.c 484 KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
527 KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
531 KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
octeon_cpunode.c 242 KASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
  /src/sys/arch/playstation2/playstation2/
locore_machdep.S 110 li t0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
  /src/sys/arch/arc/isa/
isabus.c 445 cf->sr &= ~MIPS_SR_INT_IE;

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