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Searched refs:MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK (Results 1 - 7 of 7) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_ci_baco.c	`122 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK, MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT, 0, 0x2 },`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_7_0_0_sh_mask.h	`275 #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000`
smu_7_1_1_sh_mask.h	`273 #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000`
smu_7_0_1_sh_mask.h	`273 #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000`
smu_7_1_0_sh_mask.h	`271 #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000`
smu_7_1_2_sh_mask.h	`273 #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000`
smu_7_1_3_sh_mask.h	`301 #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000`

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