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Searched refs:MISC_CLK_CTRL__ZCLK_SEL_MASK (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_ci_baco.c	`121 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x2 },`
amdgpu_fiji_baco.c	`104 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 },`
amdgpu_polaris_baco.c	`107 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 },`
amdgpu_tonga_baco.c	`112 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 },`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik.c	`1764 MISC_CLK_CTRL__ZCLK_SEL_MASK);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_7_0_0_sh_mask.h	`273 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00`
smu_7_1_1_sh_mask.h	`271 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00`
smu_7_0_1_sh_mask.h	`271 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00`
smu_7_1_0_sh_mask.h	`269 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00`
smu_7_1_2_sh_mask.h	`271 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00`
smu_7_1_3_sh_mask.h	`299 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00`

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