HomeSort by: relevance | last modified time | path
    Searched refs:MI_FLUSH_DW (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/gt/
intel_engine.h 99 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
281 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
286 *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW | flags;
intel_gpu_commands.h 149 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
intel_ring_submission.c 442 *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
462 *cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB |
473 *cs++ = MI_FLUSH_DW;
1698 static int mi_flush_dw(struct i915_request *rq, u32 flags) function in typeref:typename:int
1706 cmd = MI_FLUSH_DW;
1736 return mi_flush_dw(rq, mode & EMIT_INVALIDATE ? invflags : 0);
intel_lrc.c 3865 cmd = MI_FLUSH_DW + 1;
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_cmd_parser.c 73 * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).
344 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
388 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
425 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
488 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, S ),

Completed in 18 milliseconds