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    Searched refs:MI_LOAD_REGISTER_IMM (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
mmio_context.c 219 *cs++ = MI_LOAD_REGISTER_IMM(count);
254 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE);
281 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2);
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/
intel_ring_submission.c 1383 *cs++ = MI_LOAD_REGISTER_IMM(1);
1387 *cs++ = MI_LOAD_REGISTER_IMM(1);
1397 *cs++ = MI_LOAD_REGISTER_IMM(1);
1439 *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
1493 *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
1538 *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
intel_gpu_commands.h 135 * Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
136 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
141 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
selftest_workarounds.c 533 *cs++ = MI_LOAD_REGISTER_IMM(1);
546 *cs++ = MI_LOAD_REGISTER_IMM(1);
835 *cs++ = MI_LOAD_REGISTER_IMM(whitelist_writable_count(engine));
intel_workarounds.c 669 *cs++ = MI_LOAD_REGISTER_IMM(wal->count);
intel_lrc.c 575 *regs = MI_LOAD_REGISTER_IMM(count);
3118 *batch++ = MI_LOAD_REGISTER_IMM(1);
3193 *batch++ = MI_LOAD_REGISTER_IMM(count);
4568 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
4571 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
selftest_lrc.c 3102 *cs++ = MI_LOAD_REGISTER_IMM(1);
3971 *cs++ = MI_LOAD_REGISTER_IMM(NUM_GPR_DW);
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_cmd_parser.c 46 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
226 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
483 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
1261 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) &&
i915_perf.c 1819 *cs++ = MI_LOAD_REGISTER_IMM(1);
1837 *cs++ = MI_LOAD_REGISTER_IMM(1);
1879 *cs++ = MI_LOAD_REGISTER_IMM(2);
1948 *cs++ = MI_LOAD_REGISTER_IMM(n_lri);
2253 *cs++ = MI_LOAD_REGISTER_IMM(count);
  /src/sys/external/bsd/drm/dist/shared-core/
i915_reg.h 129 #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)
  /src/sys/external/bsd/drm2/dist/drm/i915/gem/
i915_gem_context.c 1125 *cs++ = MI_LOAD_REGISTER_IMM(2);
1147 *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED;
i915_gem_execbuffer.c 1973 *cs++ = MI_LOAD_REGISTER_IMM(4);

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