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    Searched refs:MIs (Results 1 - 10 of 10) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
InstructionSelectorImpl.h 62 bool NoFPException = !State.MIs[0]->getDesc().mayRaiseFPException();
64 const uint16_t Flags = State.MIs[0]->getFlags();
108 // As an optimisation we require that MIs[0] is always the root. Refuse
110 assert(NewInsnID != 0 && "Refusing to modify MIs[0]");
112 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
129 if ((size_t)NewInsnID < State.MIs.size())
130 State.MIs[NewInsnID] = NewMI;
132 assert((size_t)NewInsnID == State.MIs.size() &&
133 "Expected to store MIs in order");
134 State.MIs.push_back(NewMI)
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InstructionSelector.h 472 RecordedMIVector MIs;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600OptimizeVectorRegisters.cpp 239 std::vector<MachineInstr *> &MIs = (*It).second;
240 MIs.erase(llvm::find(MIs, MI), MIs.end());
244 std::vector<MachineInstr *> &MIs = (*It).second;
245 MIs.erase(llvm::find(MIs, MI), MIs.end());
302 std::vector<MachineInstr *> &MIs =
304 CompatibleRSI = PreviousRegSeq[MIs.back()]
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R600InstrInfo.h 136 /// starting from the one already provided in the Instruction Group MIs that
139 /// isLastAluTrans should be set if the last Alu of MIs will be executed on
142 /// PV holds GPR to PV registers in the Instruction Group MIs.
143 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
R600ControlFlowFinalizer.cpp 464 void CounterPropagateAddr(const std::set<MachineInstr *> &MIs,
466 for (MachineInstr *MI : MIs) {
R600InstrInfo.cpp 403 /// returns how many MIs (whose inputs are represented by IGSrcs) can be packed
585 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)
589 for (unsigned i = 0, n = MIs.size(); i < n; i++) {
590 MachineInstr &MI = *MIs[i];
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
InstructionSelector.cpp 32 : Renderers(MaxRenderers), MIs() {}
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
VirtRegMap.cpp 433 SmallVector<MachineInstr *, 2> MIs({&MI});
442 MIs.push_back(&*I);
444 MachineInstr *FirstMI = MIs.back();
460 for (int E = MIs.size(), PrevE = E; E > 1; PrevE = E) {
462 if (!anyRegsAlias(MIs[I], makeArrayRef(MIs).take_front(E), TRI)) {
464 std::swap(MIs[I], MIs[E - 1]);
475 for (MachineInstr *BundledMI : llvm::reverse(MIs)) {
MachineInstr.cpp 425 ArrayRef<const MachineInstr *> MIs) {
426 // Try handling easy numbers of MIs with simpler mechanisms.
427 if (MIs.empty()) {
431 if (MIs.size() == 1) {
432 cloneMemRefs(MF, *MIs[0]);
438 if (MIs[0]->memoperands_empty()) {
446 assert(&MF == MIs[0]->getMF() &&
448 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
450 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1)))
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineInstr.h 365 /// next 2 MIs are considered "inside" the bundle.
384 /// a bundle, but the next three MIs are.
1773 /// Note that `*this` may be one of the incoming MIs!
1778 ArrayRef<const MachineInstr *> MIs);

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