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    Searched refs:MLOAD (Results 1 - 13 of 13) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 1144 // Val, OutChain = MLOAD(BasePtr, Mask, PassThru)
1146 MLOAD,
SelectionDAGNodes.h 1384 N->getOpcode() == ISD::MLOAD ||
2309 /// This base class is used to represent MLOAD and MSTORE nodes
2327 return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
2330 return getOperand(getOpcode() == ISD::MLOAD ? 3 : 4);
2346 return N->getOpcode() == ISD::MLOAD ||
2351 /// This class is used to represent an MLOAD node
2359 : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, AM, MemVT, MMO) {
2374 return N->getOpcode() == ISD::MLOAD;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLoweringHVX.cpp 114 setOperationAction(ISD::MLOAD, T, Custom);
169 setOperationAction(ISD::MLOAD, T, Custom);
217 setOperationAction(ISD::MLOAD, BoolW, Custom);
1711 assert(Opc == ISD::MLOAD || Opc == ISD::MSTORE);
1713 if (Opc == ISD::MLOAD) {
1843 assert(MemOpc == ISD::MLOAD || MemOpc == ISD::MSTORE);
1850 if (MemOpc == ISD::MLOAD) {
2068 case ISD::MLOAD:
2121 case ISD::MLOAD:
2166 case ISD::MLOAD
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGDumper.cpp 387 case ISD::MLOAD: return "masked_load";
LegalizeIntegerTypes.cpp 72 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));
1510 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
LegalizeVectorTypes.cpp 938 case ISD::MLOAD:
3000 case ISD::MLOAD:
SelectionDAG.cpp 685 case ISD::MLOAD: {
7549 AddNodeIDNode(ID, ISD::MLOAD, VTs, Ops);
DAGCombiner.cpp 1719 case ISD::MLOAD: return visitMLOAD(N);
5611 auto *MLoad = dyn_cast<MaskedLoadSDNode>(N0);
5613 if (MLoad && BVec && MLoad->getExtensionType() == ISD::EXTLOAD &&
5615 EVT LoadVT = MLoad->getMemoryVT();
5626 ExtVT, SDLoc(N), MLoad->getChain(), MLoad->getBasePtr(),
5627 MLoad->getOffset(), MLoad->getMask(), MLoad->getPassThru()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 515 setOperationAction(ISD::MLOAD, VT, Custom);
576 setOperationAction(ISD::MLOAD, VT, Custom);
676 setOperationAction(ISD::MLOAD, VT, Custom);
755 setOperationAction(ISD::MLOAD, VT, Custom);
2333 case ISD::MLOAD:
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 1440 case ISD::MLOAD:
3795 case ISD::MLOAD:
ARMISelLowering.cpp 274 setOperationAction(ISD::MLOAD, VT, Custom);
339 setOperationAction(ISD::MLOAD, VT, Custom);
9923 case ISD::MLOAD:
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 1402 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1576 // With 512-bit vectors and no VLX, we prefer to widen MLOAD/MSTORE
1582 setOperationAction(ISD::MLOAD, VT, Custom);
1736 setOperationAction(ISD::MLOAD, VT, Legal);
1743 setOperationAction(ISD::MLOAD, VT, Legal);
1889 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
2030 setTargetDAGCombine(ISD::MLOAD);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 1198 setOperationAction(ISD::MLOAD, VT, Custom);
1489 setOperationAction(ISD::MLOAD, VT, Custom);
4677 case ISD::MLOAD:

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