HomeSort by: relevance | last modified time | path
    Searched refs:MO1 (Results 1 - 20 of 20) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMInstPrinter.cpp 101 const MCOperand &MO1 = MI->getOperand(1);
112 printRegName(O, MO1.getReg());
124 const MCOperand &MO1 = MI->getOperand(1);
134 printRegName(O, MO1.getReg());
354 const MCOperand &MO1 = MI->getOperand(OpNum);
355 if (MO1.isExpr()) {
356 MO1.getExpr()->print(O, &MAI);
362 int32_t OffImm = (int32_t)MO1.getImm();
384 const MCOperand &MO1 = MI->getOperand(OpNum);
388 printRegName(O, MO1.getReg())
    [all...]
ARMMCCodeEmitter.cpp 595 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
599 int32_t SImm = MO1.getImm();
930 const MCOperand &MO1 = MI.getOperand(OpIdx);
932 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
985 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
986 if (MO1.isImm()) {
988 } else if (MO1.isExpr()) {
994 Fixups.push_back(MCFixup::create(0, MO1.getExpr(), Kind, MI.getLoc()));
1185 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1187 unsigned Imm8 = MO1.getImm()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86OptimizeLEAs.cpp 67 static inline bool isIdenticalOp(const MachineOperand &MO1,
72 static bool isSimilarDispOp(const MachineOperand &MO1,
201 static inline bool isIdenticalOp(const MachineOperand &MO1,
203 return MO1.isIdenticalTo(MO2) &&
204 (!MO1.isReg() || !Register::isPhysicalRegister(MO1.getReg()));
214 static bool isSimilarDispOp(const MachineOperand &MO1,
216 assert(isValidDispOp(MO1) && isValidDispOp(MO2) &&
218 return (MO1.isImm() && MO2.isImm()) ||
219 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) |
    [all...]
X86RegisterInfo.cpp 901 MachineOperand &MO1 = MI->getOperand(1);
903 ShapeT Shape(&MO1, &MO2, MRI);
X86FloatingPoint.cpp 1463 const MachineOperand &MO1 = MI.getOperand(1);
1465 bool KillsSrc = MI.killsRegister(MO1.getReg());
1469 unsigned SrcFP = getFPReg(MO1);
X86InstrInfo.cpp 6359 MachineOperand &MO1 = DataMI->getOperand(1);
6360 if (MO1.getImm() == 0) {
6373 MO1.ChangeToRegister(MO0.getReg(), false);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMHazardRecognizer.cpp 200 auto MO1 = *L1->memoperands().begin();
201 auto BaseVal1 = MO1->getValue();
202 auto BasePseudoVal1 = MO1->getPseudoValue();
ARMAsmPrinter.cpp 956 const MachineOperand &MO1 = MI->getOperand(1);
957 unsigned JTI = MO1.getIndex();
1002 const MachineOperand &MO1 = MI->getOperand(1);
1003 unsigned JTI = MO1.getIndex();
1032 const MachineOperand &MO1 = MI->getOperand(1);
1033 unsigned JTI = MO1.getIndex();
ARMExpandPseudoInsts.cpp 2392 const MachineOperand &MO1 = MI.getOperand(1);
2393 auto Flags = MO1.getTargetFlags();
2394 const GlobalValue *GV = MO1.getGlobal();
2450 const MachineOperand &MO1 = MI.getOperand(1);
2451 const GlobalValue *GV = MO1.getGlobal();
2452 unsigned TF = MO1.getTargetFlags();
2463 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
2468 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
ARMBaseInstrInfo.cpp 1850 const MachineOperand &MO1 = MI1.getOperand(1);
1851 if (MO0.getOffset() != MO1.getOffset())
1861 return MO0.getGlobal() == MO1.getGlobal();
1866 int CPI1 = MO1.getIndex();
1906 const MachineOperand &MO1 = MI1.getOperand(i);
1907 if (!MO0.isIdenticalTo(MO1))
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/MCTargetDesc/
MSP430MCCodeEmitter.cpp 123 const MCOperand &MO1 = MI.getOperand(Op);
124 assert(MO1.isReg() && "Register operand expected");
125 unsigned Reg = Ctx.getRegisterInfo()->getEncodingValue(MO1.getReg());
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ExpandPseudoInsts.cpp 902 const MachineOperand &MO1 = MI.getOperand(1);
903 unsigned Flags = MO1.getTargetFlags();
910 if (MO1.isGlobal()) {
911 MIB.addGlobalAddress(MO1.getGlobal(), 0, Flags);
912 } else if (MO1.isSymbol()) {
913 MIB.addExternalSymbol(MO1.getSymbolName(), Flags);
915 assert(MO1.isCPI() &&
917 MIB.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(), Flags);
942 if (MO1.isGlobal())
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64MCCodeEmitter.cpp 264 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
265 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL &&
267 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm());
AArch64InstPrinter.cpp 1111 const MCOperand MO1 = MI->getOperand(OpNum + 1);
1113 if (MO1.isImm()) {
1114 O << ", #" << formatImm(MO1.getImm() * Scale);
1116 assert(MO1.isExpr() && "Unexpected operand type!");
1118 MO1.getExpr()->print(O, &MAI);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RegAllocFast.cpp 1187 const MachineOperand &MO1 = MI.getOperand(I1);
1189 Register Reg1 = MO1.getReg();
1208 bool Livethrough1 = MO1.isEarlyClobber() || MO1.isTied() ||
1209 (MO1.getSubReg() == 0 && !MO1.isUndef());
MachineVerifier.cpp 2562 const MachineOperand &MO1 = Phi.getOperand(I + 1);
2563 if (!MO1.isMBB()) {
2564 report("Expected PHI operand to be a basic block", &MO1, I + 1);
2568 const MachineBasicBlock &Pre = *MO1.getMBB();
2570 report("PHI input is not a predecessor block", &MO1, I + 1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonAsmPrinter.cpp 462 MCOperand &MO1 = MappedInst.getOperand(1);
463 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi);
464 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/
HexagonAsmParser.cpp 1234 static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1,
1239 TmpInst.addOperand(MO1);
1596 MCOperand &MO1 = Inst.getOperand(1);
1604 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2);
1611 MCOperand &MO1 = Inst.getOperand(1);
1613 if (MO1.getExpr()->evaluateAsAbsolute(Value)) {
1619 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 1114 MachineOperand &MO1 = MI.getOperand(1);
1115 auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1);
1116 MO1.setReg(TruncMIB.getReg(0));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIInstrInfo.cpp 409 auto MO1 = *MI1.memoperands_begin();
411 if (MO1->getAddrSpace() != MO2->getAddrSpace())
414 auto Base1 = MO1->getValue();

Completed in 129 milliseconds