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Searched refs:MOD_1 (Results 1 - 4 of 4) sorted by relevancy

/src/external/gpl3/binutils/dist/opcodes/
mips16-opc.c	171 #define MOD_1 (WR_1\|RD_1) 217 {"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, 227 {"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, 235 {"and", "x,y", 0xe80c, 0xf81f, MOD_1\|RD_2, SH, I1, 0, 0 }, 270 {"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, 277 {"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, 300 {"dsllv", "y,x", 0xe814, 0xf81f, MOD_1\|RD_2, SH, I3, 0, 0 }, 302 {"dsll", "y,x", 0xe814, 0xf81f, MOD_1\|RD_2, SH, I3, 0, 0 }, 303 {"dsrav", "y,x", 0xe817, 0xf81f, MOD_1\|RD_2, SH, I3, 0, 0 }, 304 {"dsra", "y,]", 0xe813, 0xf81f, MOD_1, 0, I3, 0, 0 } [all...]
micromips-opc.c	225 #define MOD_1 (WR_1\|RD_1) 345 {"addiu", "ms,mt,mY", 0x4c01, 0xfc01, MOD_1, 0, I1, 0, 0 }, /* addiusp / 346 {"addiu", "mp,mt,mX", 0x4c00, 0xfc01, MOD_1, 0, I1, 0, 0 }, / addius5 */ 353 {"addius5", "mp,mX", 0x4c00, 0xfc01, MOD_1, 0, I1, 0, 0 }, 360 {"and", "mf,mt,mg", 0x4480, 0xffc0, MOD_1\|RD_3, 0, I1, 0, 0 }, 361 {"and", "mf,mg,mx", 0x4480, 0xffc0, MOD_1\|RD_2, 0, I1, 0, 0 }, 997 {"or", "mf,mt,mg", 0x44c0, 0xffc0, MOD_1\|RD_3, 0, I1, 0, 0 }, 998 {"or", "mf,mg,mx", 0x44c0, 0xffc0, MOD_1\|RD_2, 0, I1, 0, 0 }, 1038 {"sc", "t,~(b)", 0x6000b000, 0xfc00f000, MOD_1\|RD_3\|SM, 0, I1, 0, 0 }, 1040 {"scd", "t,~(b)", 0x6000f000, 0xfc00f000, MOD_1\|RD_3\|SM, 0, I3, 0, 0 } [all...]
/src/external/gpl3/binutils.old/dist/opcodes/
mips16-opc.c	171 #define MOD_1 (WR_1\|RD_1) 217 {"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, 227 {"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, 235 {"and", "x,y", 0xe80c, 0xf81f, MOD_1\|RD_2, SH, I1, 0, 0 }, 270 {"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, 277 {"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, 300 {"dsllv", "y,x", 0xe814, 0xf81f, MOD_1\|RD_2, SH, I3, 0, 0 }, 302 {"dsll", "y,x", 0xe814, 0xf81f, MOD_1\|RD_2, SH, I3, 0, 0 }, 303 {"dsrav", "y,x", 0xe817, 0xf81f, MOD_1\|RD_2, SH, I3, 0, 0 }, 304 {"dsra", "y,]", 0xe813, 0xf81f, MOD_1, 0, I3, 0, 0 } [all...]
micromips-opc.c	225 #define MOD_1 (WR_1\|RD_1) 345 {"addiu", "ms,mt,mY", 0x4c01, 0xfc01, MOD_1, 0, I1, 0, 0 }, /* addiusp / 346 {"addiu", "mp,mt,mX", 0x4c00, 0xfc01, MOD_1, 0, I1, 0, 0 }, / addius5 */ 353 {"addius5", "mp,mX", 0x4c00, 0xfc01, MOD_1, 0, I1, 0, 0 }, 360 {"and", "mf,mt,mg", 0x4480, 0xffc0, MOD_1\|RD_3, 0, I1, 0, 0 }, 361 {"and", "mf,mg,mx", 0x4480, 0xffc0, MOD_1\|RD_2, 0, I1, 0, 0 }, 997 {"or", "mf,mt,mg", 0x44c0, 0xffc0, MOD_1\|RD_3, 0, I1, 0, 0 }, 998 {"or", "mf,mg,mx", 0x44c0, 0xffc0, MOD_1\|RD_2, 0, I1, 0, 0 }, 1038 {"sc", "t,~(b)", 0x6000b000, 0xfc00f000, MOD_1\|RD_3\|SM, 0, I1, 0, 0 }, 1040 {"scd", "t,~(b)", 0x6000f000, 0xfc00f000, MOD_1\|RD_3\|SM, 0, I3, 0, 0 } [all...]

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