1 /* $NetBSD: mpc5200reg.h,v 1.1 2026/06/27 13:28:35 rkujawa Exp $ */ 2 3 /*- 4 * Copyright (c) 2026 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa and Robert Swindells. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _POWERPC_MPC5200_MPC5200REG_H_ 33 #define _POWERPC_MPC5200_MPC5200REG_H_ 34 35 /* 36 * On-chip peripheral register map for the Freescale MPC5200B. 37 */ 38 39 #define MPC5200_MBAR_DEFAULT 0xf0000000 /* firmware default MBAR */ 40 #define MPC5200_MBAR_SIZE 0x00010000 /* 64KB peripheral window */ 41 42 /* MBAR-relative block offsets. */ 43 #define MPC5200_REG_MBAR 0x0000 /* MBAR / arbiter config */ 44 #define MPC5200_REG_SDRAM 0x0100 /* SDRAM/DDR memory controller */ 45 #define MPC5200_REG_CDM 0x0200 /* clock distribution module */ 46 #define MPC5200_REG_SIU 0x0500 /* SIU interrupt controller */ 47 #define MPC5200_REG_GPT 0x0600 /* general purpose timers 0-7 */ 48 #define MPC5200_REG_SLT 0x0700 /* slice timers */ 49 #define MPC5200_REG_RTC 0x0800 /* real-time clock */ 50 #define MPC5200_REG_MSCAN1 0x0900 /* CAN 1 */ 51 #define MPC5200_REG_MSCAN2 0x0980 /* CAN 2 */ 52 #define MPC5200_REG_GPIO 0x0b00 /* simple GPIO */ 53 #define MPC5200_REG_GPIO_WKUP 0x0c00 /* wakeup GPIO */ 54 #define MPC5200_REG_PCI 0x0d00 /* PCI controller */ 55 #define MPC5200_REG_SPI 0x0f00 /* dedicated SPI */ 56 #define MPC5200_REG_USB 0x1000 /* USB OHCI */ 57 #define MPC5200_REG_SDMA 0x1200 /* BestComm SDMA */ 58 #define MPC5200_REG_XLB 0x1f00 /* XLB arbiter */ 59 #define MPC5200_REG_PSC1 0x2000 /* PSC1 (console UART) */ 60 #define MPC5200_REG_PSC2 0x2200 /* PSC2 (AC97 codec) */ 61 #define MPC5200_REG_PSC3 0x2400 /* PSC3 */ 62 #define MPC5200_REG_PSC4 0x2600 /* PSC4 */ 63 #define MPC5200_REG_PSC5 0x2800 /* PSC5 */ 64 #define MPC5200_REG_PSC6 0x2c00 /* PSC6 */ 65 #define MPC5200_REG_FEC 0x3000 /* fast ethernet controller */ 66 #define MPC5200_REG_ATA 0x3a00 /* ATA controller */ 67 #define MPC5200_REG_I2C1 0x3d00 /* I2C 1 */ 68 #define MPC5200_REG_I2C2 0x3d40 /* I2C 2 */ 69 #define MPC5200_REG_SRAM 0x8000 /* on-chip SRAM (16KB) */ 70 71 #define MPC5200_PSC_SIZE 0x100 /* per-PSC register window */ 72 #define MPC5200_SRAM_SIZE 0x4000 /* on-chip SRAM size (16KB) */ 73 #define MPC5200_USB_SIZE 0x200 /* USB OHCI register window */ 74 75 #endif /* _POWERPC_MPC5200_MPC5200REG_H_ */ 76
Indexes created Wed Jul 01 00:25:26 UTC 2026