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Searched refs:MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_polaris_baco.c	`73 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 }, 113 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 } 165 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 }`
amdgpu_ci_baco.c	`85 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 }, 118 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 },`
amdgpu_fiji_baco.c	`83 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 } 101 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 },`
amdgpu_tonga_baco.c	`83 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 }, 109 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 },`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik.c	`1781 data &= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK;`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_7_0_0_sh_mask.h	`233 #define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00`
smu_7_1_1_sh_mask.h	`223 #define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00`
smu_7_0_1_sh_mask.h	`225 #define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00`
smu_7_1_0_sh_mask.h	`223 #define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00`
smu_7_1_2_sh_mask.h	`225 #define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00`
smu_7_1_3_sh_mask.h	`251 #define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00`

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