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    Searched refs:MPLL_FREQ_LEVEL_0 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
rv6xxd.h	80 #define MPLL_FREQ_LEVEL_0 0x6e8
radeon_rv6xx_dpm.c	378 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 381 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0, ~LEVEL0_MPLL_DIV_EN); 387 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 394 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider), 401 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),

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Indexes created Thu Oct 16 14:10:15 GMT 2025