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Searched refs:MSA (Results 1 - 5 of 5) sorted by relevancy

/src/external/gpl3/binutils/dist/opcodes/
micromips-opc.c	116 case 'd': REG (5, 6, MSA); 117 case 'e': REG (5, 11, MSA); 118 case 'h': REG (5, 16, MSA); 291 /* MSA support. / 292 #define MSA ASE_MSA 1403 / MSA Extension. */ 1404 {"sll.b", "+d,+e,+h", 0x5800001a, 0xffe0003f, WR_1\|RD_2\|RD_3, 0, 0, MSA, 0 }, 1405 {"sll.h", "+d,+e,+h", 0x5820001a, 0xffe0003f, WR_1\|RD_2\|RD_3, 0, 0, MSA, 0 }, 1406 {"sll.w", "+d,+e,+h", 0x5840001a, 0xffe0003f, WR_1\|RD_2\|RD_3, 0, 0, MSA, 0 }, 1407 {"sll.d", "+d,+e,+h", 0x5860001a, 0xffe0003f, WR_1\|RD_2\|RD_3, 0, 0, MSA, 0 } [all...]
mips-opc.c	104 case 'd': REG (5, 6, MSA); 105 case 'e': REG (5, 11, MSA); 108 case 'h': REG (5, 16, MSA); 405 /* MSA support. / 406 #define MSA ASE_MSA 2616 / MSA Extension. */ 2617 {"sll.b", "+d,+e,+h", 0x7800000d, 0xffe0003f, WR_1\|RD_2\|RD_3, 0, 0, MSA, 0 }, 2618 {"sll.h", "+d,+e,+h", 0x7820000d, 0xffe0003f, WR_1\|RD_2\|RD_3, 0, 0, MSA, 0 }, 2619 {"sll.w", "+d,+e,+h", 0x7840000d, 0xffe0003f, WR_1\|RD_2\|RD_3, 0, 0, MSA, 0 }, 2620 {"sll.d", "+d,+e,+h", 0x7860000d, 0xffe0003f, WR_1\|RD_2\|RD_3, 0, 0, MSA, 0 } [all...]
/src/external/gpl3/binutils.old/dist/opcodes/
micromips-opc.c	116 case 'd': REG (5, 6, MSA); 117 case 'e': REG (5, 11, MSA); 118 case 'h': REG (5, 16, MSA); 291 /* MSA support. / 292 #define MSA ASE_MSA 1403 / MSA Extension. */ 1404 {"sll.b", "+d,+e,+h", 0x5800001a, 0xffe0003f, WR_1\|RD_2\|RD_3, 0, 0, MSA, 0 }, 1405 {"sll.h", "+d,+e,+h", 0x5820001a, 0xffe0003f, WR_1\|RD_2\|RD_3, 0, 0, MSA, 0 }, 1406 {"sll.w", "+d,+e,+h", 0x5840001a, 0xffe0003f, WR_1\|RD_2\|RD_3, 0, 0, MSA, 0 }, 1407 {"sll.d", "+d,+e,+h", 0x5860001a, 0xffe0003f, WR_1\|RD_2\|RD_3, 0, 0, MSA, 0 } [all...]
mips-opc.c	104 case 'd': REG (5, 6, MSA); 105 case 'e': REG (5, 11, MSA); 108 case 'h': REG (5, 16, MSA); 405 /* MSA support. / 406 #define MSA ASE_MSA 2616 / MSA Extension. */ 2617 {"sll.b", "+d,+e,+h", 0x7800000d, 0xffe0003f, WR_1\|RD_2\|RD_3, 0, 0, MSA, 0 }, 2618 {"sll.h", "+d,+e,+h", 0x7820000d, 0xffe0003f, WR_1\|RD_2\|RD_3, 0, 0, MSA, 0 }, 2619 {"sll.w", "+d,+e,+h", 0x7840000d, 0xffe0003f, WR_1\|RD_2\|RD_3, 0, 0, MSA, 0 }, 2620 {"sll.d", "+d,+e,+h", 0x7860000d, 0xffe0003f, WR_1\|RD_2\|RD_3, 0, 0, MSA, 0 } [all...]
/src/external/apache2/llvm/dist/llvm/lib/ObjectYAML/
ELFYAML.cpp	`977 BCase(MSA);`

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