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  /src/sys/arch/powerpc/oea/
kgdb_glue.c 78 kgdbregs[MSR] &= ~PSL_BE;
83 kgdbregs[MSR] &= ~PSL_SE;
86 kgdbregs[MSR] |= PSL_SE;
  /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Checkers/cert/
PutenvWithAutoChecker.cpp 46 const MemSpaceRegion *MSR = ArgV.getAsRegion()->getMemorySpace();
48 if (!isa<StackSpaceRegion>(MSR))
  /src/external/gpl3/gdb/dist/sim/microblaze/
microblaze.h 50 #define MSR CPU.spregs[1]
72 #define C_rd ((MSR & 0x4) >> 2)
73 #define C_wr(D) MSR = (D ? MSR | 0x80000004 : MSR & 0x7FFFFFFB)
microblaze.isa 394 MSR = MSR | BIP_MASK;
564 MSR = MSR | INTR_EN_MASK;
572 MSR = MSR & ~BIP_MASK;
623 MSR = MSR | BIP_MASK;
  /src/external/gpl3/gdb.old/dist/sim/microblaze/
microblaze.h 50 #define MSR CPU.spregs[1]
72 #define C_rd ((MSR & 0x4) >> 2)
73 #define C_wr(D) MSR = (D ? MSR | 0x80000004 : MSR & 0x7FFFFFFB)
microblaze.isa 394 MSR = MSR | BIP_MASK;
564 MSR = MSR | INTR_EN_MASK;
572 MSR = MSR & ~BIP_MASK;
623 MSR = MSR | BIP_MASK;
  /src/sys/arch/bebox/include/
kgdb.h 40 #define MSR 37
  /src/sys/arch/ibmnws/include/
kgdb.h 40 #define MSR 37
  /src/sys/arch/mvmeppc/include/
kgdb.h 40 #define MSR 37
  /src/sys/arch/prep/include/
kgdb.h 40 #define MSR 37
  /src/sys/arch/rs6000/include/
kgdb.h 40 #define MSR 37
  /src/sys/arch/sandpoint/include/
kgdb.h 40 #define MSR 37
  /src/sys/arch/sparc64/sparc64/
bsd_fdintr.s 98 ld [R_fdc + FDC_REG_MSR], R_msr ! get chip MSR reg addr
115 ldub [R_msr], %l7 ! get MSR value
141 ldub [R_msr], %l7 ! get MSR value
  /src/external/gpl3/gdb/dist/gdb/arch/
aarch64-insn.h 127 /* MSR (register) 1101 0101 0001 oooo oooo oooo ooor rrrr */
129 MSR = 0xd5100000,
130 MRS = 0x00200000 | MSR,
  /src/external/gpl3/gdb.old/dist/gdb/arch/
aarch64-insn.h 127 /* MSR (register) 1101 0101 0001 oooo oooo oooo ooor rrrr */
129 MSR = 0xd5100000,
130 MRS = 0x00200000 | MSR,
  /src/sys/arch/sparc/sparc/
bsd_fdintr.s 189 ld [R_fdc + FDC_REG_MSR], R_msr ! get chip MSR reg addr
212 ldub [R_msr], %l7 ! get MSR value
249 ldub [R_msr], %l7 ! get MSR value
  /src/sys/external/mit/xen-include-public/dist/xen/include/public/arch-x86/
cpufeatureset.h 98 XEN_CPUFEATURE(MSR, 0*32+ 5) /*A Model-Specific Registers, RDMSR, WRMSR */
112 XEN_CPUFEATURE(ACPI, 0*32+22) /*A ACPI via MSR */
136 XEN_CPUFEATURE(PDCM, 1*32+15) /* Perf/Debug Capability MSR */
181 XEN_CPUFEATURE(NODEID_MSR, 3*32+19) /* NodeId MSR */
195 XEN_CPUFEATURE(TSC_ADJUST, 5*32+ 1) /*S TSC_ADJUST MSR available */
248 XEN_CPUFEATURE(ARCH_CAPS, 9*32+29) /* IA32_ARCH_CAPABILITIES MSR */
  /src/external/gpl3/gdb/dist/sim/ppc/
e500_expression.h 145 if (MSR & msr_e500_spu_enable) { \
interrupts.c 82 interrupt_base_ea(msreg msr)
84 if (msr & msr_interrupt_prefix)
104 msreg old_msr = MSR;
109 "double interrupt - MSR[RI] bit clear when attempting to deliver interrupt, cia=0x%lx, msr=0x%lx; srr0=0x%lx(cia), srr1=0x%lx(msr); trap-vector=0x%lx, trap-msr=0x%lx",
119 MSR = new_msr;
439 been enabled through changes to the MSR. */
448 if ((cpu_registers(processor)->msr & (msr_floating_point_exception_mode_
    [all...]
idecode_expression.h 338 if ((MSR & (msr_floating_point_exception_mode_0 \
registers.h 270 msreg msr; member in struct:_registers
342 #define MSR cpu_registers(processor)->msr
  /src/external/gpl3/gdb.old/dist/sim/ppc/
e500_expression.h 145 if (MSR & msr_e500_spu_enable) { \
interrupts.c 82 interrupt_base_ea(msreg msr)
84 if (msr & msr_interrupt_prefix)
104 msreg old_msr = MSR;
109 "double interrupt - MSR[RI] bit clear when attempting to deliver interrupt, cia=0x%lx, msr=0x%lx; srr0=0x%lx(cia), srr1=0x%lx(msr); trap-vector=0x%lx, trap-msr=0x%lx",
119 MSR = new_msr;
439 been enabled through changes to the MSR. */
448 if ((cpu_registers(processor)->msr & (msr_floating_point_exception_mode_
    [all...]
idecode_expression.h 338 if ((MSR & (msr_floating_point_exception_mode_0 \
  /src/sys/dev/pcmcia/
if_xireg.h 111 #define MSR 0xc /* RW - Misc. setup register */
229 /* MSR register bits */

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