1 /* $NetBSD: if_mue.c,v 1.84 2025/10/04 04:44:21 thorpej Exp $ */ 2 /* $OpenBSD: if_mue.c,v 1.3 2018/08/04 16:42:46 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2018 Kevin Lo <kevlo (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* Driver for Microchip LAN7500/LAN7800 chipsets. */ 21 22 #include <sys/cdefs.h> 23 __KERNEL_RCSID(0, "$NetBSD: if_mue.c,v 1.84 2025/10/04 04:44:21 thorpej Exp $"); 24 25 #ifdef _KERNEL_OPT 26 #include "opt_usb.h" 27 #include "opt_inet.h" 28 #endif 29 30 #include <sys/param.h> 31 32 #include <dev/usb/usbnet.h> 33 34 #include <dev/usb/if_muereg.h> 35 #include <dev/usb/if_muevar.h> 36 37 #define MUE_PRINTF(un, fmt, args...) \ 38 device_printf((un)->un_dev, "%s: " fmt, __func__, ##args); 39 40 #ifdef USB_DEBUG 41 int muedebug = 0; 42 #define DPRINTF(un, fmt, args...) \ 43 do { \ 44 if (muedebug) \ 45 MUE_PRINTF(un, fmt, ##args); \ 46 } while (0 /* CONSTCOND */) 47 #else 48 #define DPRINTF(un, fmt, args...) __nothing 49 #endif 50 51 /* 52 * Various supported device vendors/products. 53 */ 54 struct mue_type { 55 struct usb_devno mue_dev; 56 uint16_t mue_flags; 57 #define LAN7500 0x0001 /* LAN7500 */ 58 #define LAN7800 0x0002 /* LAN7800 */ 59 #define LAN7801 0x0004 /* LAN7801 */ 60 #define LAN7850 0x0008 /* LAN7850 */ 61 }; 62 63 static const struct mue_type mue_devs[] = { 64 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7500 }, LAN7500 }, 65 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7505 }, LAN7500 }, 66 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7800 }, LAN7800 }, 67 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7801 }, LAN7801 }, 68 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7850 }, LAN7850 } 69 }; 70 71 #define MUE_LOOKUP(uaa) ((const struct mue_type *)usb_lookup(mue_devs, \ 72 uaa->uaa_vendor, uaa->uaa_product)) 73 74 #define MUE_ENADDR_LO(enaddr) \ 75 ((enaddr[3] << 24) | (enaddr[2] << 16) | (enaddr[1] << 8) | enaddr[0]) 76 #define MUE_ENADDR_HI(enaddr) \ 77 ((enaddr[5] << 8) | enaddr[4]) 78 79 static int mue_match(device_t, cfdata_t, void *); 80 static void mue_attach(device_t, device_t, void *); 81 82 static uint32_t mue_csr_read(struct usbnet *, uint32_t); 83 static int mue_csr_write(struct usbnet *, uint32_t, uint32_t); 84 static int mue_wait_for_bits(struct usbnet *, uint32_t, uint32_t, 85 uint32_t, uint32_t); 86 static uint8_t mue_eeprom_getbyte(struct usbnet *, int, uint8_t *); 87 static bool mue_eeprom_present(struct usbnet *); 88 static void mue_dataport_write(struct usbnet *, uint32_t, uint32_t, 89 uint32_t, uint32_t *); 90 static void mue_init_ltm(struct usbnet *); 91 static int mue_chip_init(struct usbnet *); 92 static void mue_set_macaddr(struct usbnet *); 93 static int mue_get_macaddr(struct usbnet *); 94 static int mue_prepare_tso(struct usbnet *, struct mbuf *); 95 static void mue_uno_mcast(struct ifnet *); 96 static void mue_sethwcsum_locked(struct usbnet *); 97 static void mue_setmtu_locked(struct usbnet *); 98 static void mue_reset(struct usbnet *); 99 100 static void mue_uno_stop(struct ifnet *, int); 101 static int mue_uno_ioctl(struct ifnet *, u_long, void *); 102 static int mue_uno_mii_read_reg(struct usbnet *, int, int, uint16_t *); 103 static int mue_uno_mii_write_reg(struct usbnet *, int, int, uint16_t); 104 static void mue_uno_mii_statchg(struct ifnet *); 105 static void mue_uno_rx_loop(struct usbnet *, struct usbnet_chain *, 106 uint32_t); 107 static unsigned mue_uno_tx_prepare(struct usbnet *, struct mbuf *, 108 struct usbnet_chain *); 109 static int mue_uno_init(struct ifnet *); 110 111 static const struct usbnet_ops mue_ops = { 112 .uno_stop = mue_uno_stop, 113 .uno_ioctl = mue_uno_ioctl, 114 .uno_mcast = mue_uno_mcast, 115 .uno_read_reg = mue_uno_mii_read_reg, 116 .uno_write_reg = mue_uno_mii_write_reg, 117 .uno_statchg = mue_uno_mii_statchg, 118 .uno_tx_prepare = mue_uno_tx_prepare, 119 .uno_rx_loop = mue_uno_rx_loop, 120 .uno_init = mue_uno_init, 121 }; 122 123 #define MUE_SETBIT(un, reg, x) \ 124 mue_csr_write(un, reg, mue_csr_read(un, reg) | (x)) 125 126 #define MUE_CLRBIT(un, reg, x) \ 127 mue_csr_write(un, reg, mue_csr_read(un, reg) & ~(x)) 128 129 #define MUE_WAIT_SET(un, reg, set, fail) \ 130 mue_wait_for_bits(un, reg, set, ~0, fail) 131 132 #define MUE_WAIT_CLR(un, reg, clear, fail) \ 133 mue_wait_for_bits(un, reg, 0, clear, fail) 134 135 #define ETHER_IS_VALID(addr) \ 136 (!ETHER_IS_MULTICAST(addr) && !ETHER_IS_ZERO(addr)) 137 138 #define ETHER_IS_ZERO(addr) \ 139 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) 140 141 CFATTACH_DECL_NEW(mue, sizeof(struct usbnet), mue_match, mue_attach, 142 usbnet_detach, usbnet_activate); 143 144 static uint32_t 145 mue_csr_read(struct usbnet *un, uint32_t reg) 146 { 147 usb_device_request_t req; 148 usbd_status err; 149 uDWord val; 150 151 if (usbnet_isdying(un)) 152 return 0; 153 154 USETDW(val, 0); 155 req.bmRequestType = UT_READ_VENDOR_DEVICE; 156 req.bRequest = MUE_UR_READREG; 157 USETW(req.wValue, 0); 158 USETW(req.wIndex, reg); 159 USETW(req.wLength, 4); 160 161 err = usbd_do_request(un->un_udev, &req, &val); 162 if (err) { 163 MUE_PRINTF(un, "reg = %#x: %s\n", reg, usbd_errstr(err)); 164 return 0; 165 } 166 167 return UGETDW(val); 168 } 169 170 static int 171 mue_csr_write(struct usbnet *un, uint32_t reg, uint32_t aval) 172 { 173 usb_device_request_t req; 174 usbd_status err; 175 uDWord val; 176 177 if (usbnet_isdying(un)) 178 return 0; 179 180 USETDW(val, aval); 181 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 182 req.bRequest = MUE_UR_WRITEREG; 183 USETW(req.wValue, 0); 184 USETW(req.wIndex, reg); 185 USETW(req.wLength, 4); 186 187 err = usbd_do_request(un->un_udev, &req, &val); 188 if (err) { 189 MUE_PRINTF(un, "reg = %#x: %s\n", reg, usbd_errstr(err)); 190 return -1; 191 } 192 193 return 0; 194 } 195 196 static int 197 mue_wait_for_bits(struct usbnet *un, uint32_t reg, 198 uint32_t set, uint32_t clear, uint32_t fail) 199 { 200 uint32_t val; 201 int ntries; 202 203 for (ntries = 0; ntries < 1000; ntries++) { 204 if (usbnet_isdying(un)) 205 return 1; 206 val = mue_csr_read(un, reg); 207 if ((val & set) || !(val & clear)) 208 return 0; 209 if (val & fail) 210 return 1; 211 usbd_delay_ms(un->un_udev, 1); 212 } 213 214 return 1; 215 } 216 217 static int 218 mue_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 219 { 220 uint32_t data; 221 222 if (un->un_phyno != phy) { 223 *val = 0; 224 return EINVAL; 225 } 226 227 if (MUE_WAIT_CLR(un, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) { 228 MUE_PRINTF(un, "not ready\n"); 229 *val = 0; 230 return EBUSY; 231 } 232 233 mue_csr_write(un, MUE_MII_ACCESS, MUE_MII_ACCESS_READ | 234 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) | 235 MUE_MII_ACCESS_PHYADDR(phy)); 236 237 if (MUE_WAIT_CLR(un, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) { 238 MUE_PRINTF(un, "timed out\n"); 239 *val = 0; 240 return ETIMEDOUT; 241 } 242 243 data = mue_csr_read(un, MUE_MII_DATA); 244 *val = data & 0xffff; 245 246 return 0; 247 } 248 249 static int 250 mue_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 251 { 252 253 if (un->un_phyno != phy) 254 return EINVAL; 255 256 if (MUE_WAIT_CLR(un, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) { 257 MUE_PRINTF(un, "not ready\n"); 258 return EBUSY; 259 } 260 261 mue_csr_write(un, MUE_MII_DATA, val); 262 mue_csr_write(un, MUE_MII_ACCESS, MUE_MII_ACCESS_WRITE | 263 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) | 264 MUE_MII_ACCESS_PHYADDR(phy)); 265 266 if (MUE_WAIT_CLR(un, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) { 267 MUE_PRINTF(un, "timed out\n"); 268 return ETIMEDOUT; 269 } 270 271 return 0; 272 } 273 274 static void 275 mue_uno_mii_statchg(struct ifnet *ifp) 276 { 277 struct usbnet * const un = ifp->if_softc; 278 struct mii_data * const mii = usbnet_mii(un); 279 uint32_t flow, threshold; 280 281 if (usbnet_isdying(un)) 282 return; 283 284 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 285 (IFM_ACTIVE | IFM_AVALID)) { 286 switch (IFM_SUBTYPE(mii->mii_media_active)) { 287 case IFM_10_T: 288 case IFM_100_TX: 289 case IFM_1000_T: 290 usbnet_set_link(un, true); 291 break; 292 default: 293 break; 294 } 295 } 296 297 /* Lost link, do nothing. */ 298 if (!usbnet_havelink(un)) { 299 DPRINTF(un, "mii_media_status = %#x\n", mii->mii_media_status); 300 return; 301 } 302 303 if (!(un->un_flags & LAN7500)) { 304 if (un->un_udev->ud_speed == USB_SPEED_SUPER) { 305 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 306 /* Disable U2 and enable U1. */ 307 MUE_CLRBIT(un, MUE_USB_CFG1, 308 MUE_USB_CFG1_DEV_U2_INIT_EN); 309 MUE_SETBIT(un, MUE_USB_CFG1, 310 MUE_USB_CFG1_DEV_U1_INIT_EN); 311 } else { 312 /* Enable U1 and U2. */ 313 MUE_SETBIT(un, MUE_USB_CFG1, 314 MUE_USB_CFG1_DEV_U1_INIT_EN | 315 MUE_USB_CFG1_DEV_U2_INIT_EN); 316 } 317 } 318 } 319 320 flow = 0; 321 /* XXX Linux does not check IFM_FDX flag for 7800. */ 322 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) { 323 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) 324 flow |= MUE_FLOW_TX_FCEN | MUE_FLOW_PAUSE_TIME; 325 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) 326 flow |= MUE_FLOW_RX_FCEN; 327 } 328 329 /* XXX Magic numbers taken from Linux driver. */ 330 if (un->un_flags & LAN7500) 331 threshold = 0x820; 332 else 333 switch (un->un_udev->ud_speed) { 334 case USB_SPEED_SUPER: 335 threshold = 0x817; 336 break; 337 case USB_SPEED_HIGH: 338 threshold = 0x211; 339 break; 340 default: 341 threshold = 0; 342 break; 343 } 344 345 /* Threshold value should be set before enabling flow. */ 346 mue_csr_write(un, (un->un_flags & LAN7500) ? 347 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, threshold); 348 mue_csr_write(un, MUE_FLOW, flow); 349 350 DPRINTF(un, "done\n"); 351 } 352 353 static uint8_t 354 mue_eeprom_getbyte(struct usbnet *un, int off, uint8_t *dest) 355 { 356 uint32_t val; 357 358 if (MUE_WAIT_CLR(un, MUE_E2P_CMD, MUE_E2P_CMD_BUSY, 0)) { 359 MUE_PRINTF(un, "not ready\n"); 360 return ETIMEDOUT; 361 } 362 363 KASSERT((off & ~MUE_E2P_CMD_ADDR_MASK) == 0); 364 mue_csr_write(un, MUE_E2P_CMD, MUE_E2P_CMD_READ | MUE_E2P_CMD_BUSY | 365 off); 366 367 if (MUE_WAIT_CLR(un, MUE_E2P_CMD, MUE_E2P_CMD_BUSY, 368 MUE_E2P_CMD_TIMEOUT)) { 369 MUE_PRINTF(un, "timed out\n"); 370 return ETIMEDOUT; 371 } 372 373 val = mue_csr_read(un, MUE_E2P_DATA); 374 *dest = val & 0xff; 375 376 return 0; 377 } 378 379 static int 380 mue_read_eeprom(struct usbnet *un, uint8_t *dest, int off, int cnt) 381 { 382 uint32_t val = 0; /* XXX gcc */ 383 uint8_t byte; 384 int i, err = 0; 385 386 /* 387 * EEPROM pins are muxed with the LED function on LAN7800 device. 388 */ 389 if (un->un_flags & LAN7800) { 390 val = mue_csr_read(un, MUE_HW_CFG); 391 mue_csr_write(un, MUE_HW_CFG, 392 val & ~(MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN)); 393 } 394 395 for (i = 0; i < cnt; i++) { 396 err = mue_eeprom_getbyte(un, off + i, &byte); 397 if (err) 398 break; 399 *(dest + i) = byte; 400 } 401 402 if (un->un_flags & LAN7800) 403 mue_csr_write(un, MUE_HW_CFG, val); 404 405 return err ? 1 : 0; 406 } 407 408 static bool 409 mue_eeprom_present(struct usbnet *un) 410 { 411 uint32_t val; 412 uint8_t sig; 413 int ret; 414 415 if (un->un_flags & LAN7500) { 416 val = mue_csr_read(un, MUE_E2P_CMD); 417 return val & MUE_E2P_CMD_LOADED; 418 } else { 419 ret = mue_read_eeprom(un, &sig, MUE_E2P_IND_OFFSET, 1); 420 return (ret == 0) && (sig == MUE_E2P_IND); 421 } 422 } 423 424 static int 425 mue_read_otp_raw(struct usbnet *un, uint8_t *dest, int off, int cnt) 426 { 427 uint32_t val; 428 int i, err; 429 430 val = mue_csr_read(un, MUE_OTP_PWR_DN); 431 432 /* Checking if bit is set. */ 433 if (val & MUE_OTP_PWR_DN_PWRDN_N) { 434 /* Clear it, then wait for it to be cleared. */ 435 mue_csr_write(un, MUE_OTP_PWR_DN, 0); 436 err = MUE_WAIT_CLR(un, MUE_OTP_PWR_DN, MUE_OTP_PWR_DN_PWRDN_N, 437 0); 438 if (err) { 439 MUE_PRINTF(un, "not ready\n"); 440 return 1; 441 } 442 } 443 444 /* Start reading the bytes, one at a time. */ 445 for (i = 0; i < cnt; i++) { 446 mue_csr_write(un, MUE_OTP_ADDR1, 447 ((off + i) >> 8) & MUE_OTP_ADDR1_MASK); 448 mue_csr_write(un, MUE_OTP_ADDR2, 449 ((off + i) & MUE_OTP_ADDR2_MASK)); 450 mue_csr_write(un, MUE_OTP_FUNC_CMD, MUE_OTP_FUNC_CMD_READ); 451 mue_csr_write(un, MUE_OTP_CMD_GO, MUE_OTP_CMD_GO_GO); 452 453 err = MUE_WAIT_CLR(un, MUE_OTP_STATUS, MUE_OTP_STATUS_BUSY, 0); 454 if (err) { 455 MUE_PRINTF(un, "timed out\n"); 456 return 1; 457 } 458 val = mue_csr_read(un, MUE_OTP_RD_DATA); 459 *(dest + i) = (uint8_t)(val & 0xff); 460 } 461 462 return 0; 463 } 464 465 static int 466 mue_read_otp(struct usbnet *un, uint8_t *dest, int off, int cnt) 467 { 468 uint8_t sig; 469 int err; 470 471 if (un->un_flags & LAN7500) 472 return 1; 473 474 err = mue_read_otp_raw(un, &sig, MUE_OTP_IND_OFFSET, 1); 475 if (err) 476 return 1; 477 switch (sig) { 478 case MUE_OTP_IND_1: 479 break; 480 case MUE_OTP_IND_2: 481 off += 0x100; 482 break; 483 default: 484 DPRINTF(un, "OTP not found\n"); 485 return 1; 486 } 487 err = mue_read_otp_raw(un, dest, off, cnt); 488 return err; 489 } 490 491 static void 492 mue_dataport_write(struct usbnet *un, uint32_t sel, uint32_t addr, 493 uint32_t cnt, uint32_t *data) 494 { 495 uint32_t i; 496 497 if (MUE_WAIT_SET(un, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) { 498 MUE_PRINTF(un, "not ready\n"); 499 return; 500 } 501 502 mue_csr_write(un, MUE_DP_SEL, 503 (mue_csr_read(un, MUE_DP_SEL) & ~MUE_DP_SEL_RSEL_MASK) | sel); 504 505 for (i = 0; i < cnt; i++) { 506 mue_csr_write(un, MUE_DP_ADDR, addr + i); 507 mue_csr_write(un, MUE_DP_DATA, data[i]); 508 mue_csr_write(un, MUE_DP_CMD, MUE_DP_CMD_WRITE); 509 if (MUE_WAIT_SET(un, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) { 510 MUE_PRINTF(un, "timed out\n"); 511 return; 512 } 513 } 514 } 515 516 static void 517 mue_init_ltm(struct usbnet *un) 518 { 519 uint32_t idx[MUE_NUM_LTM_INDEX] = { 0, 0, 0, 0, 0, 0 }; 520 uint8_t temp[2]; 521 size_t i; 522 523 if (mue_csr_read(un, MUE_USB_CFG1) & MUE_USB_CFG1_LTM_ENABLE) { 524 if (mue_eeprom_present(un) && 525 (mue_read_eeprom(un, temp, MUE_E2P_LTM_OFFSET, 2) == 0)) { 526 if (temp[0] != sizeof(idx)) { 527 DPRINTF(un, "EEPROM: unexpected size\n"); 528 goto done; 529 } 530 if (mue_read_eeprom(un, (uint8_t *)idx, temp[1] << 1, 531 sizeof(idx))) { 532 DPRINTF(un, "EEPROM: failed to read\n"); 533 goto done; 534 } 535 DPRINTF(un, "success\n"); 536 } else if (mue_read_otp(un, temp, MUE_E2P_LTM_OFFSET, 2) == 0) { 537 if (temp[0] != sizeof(idx)) { 538 DPRINTF(un, "OTP: unexpected size\n"); 539 goto done; 540 } 541 if (mue_read_otp(un, (uint8_t *)idx, temp[1] << 1, 542 sizeof(idx))) { 543 DPRINTF(un, "OTP: failed to read\n"); 544 goto done; 545 } 546 DPRINTF(un, "success\n"); 547 } else 548 DPRINTF(un, "nothing to do\n"); 549 } else 550 DPRINTF(un, "nothing to do\n"); 551 done: 552 for (i = 0; i < __arraycount(idx); i++) 553 mue_csr_write(un, MUE_LTM_INDEX(i), idx[i]); 554 } 555 556 static int 557 mue_chip_init(struct usbnet *un) 558 { 559 uint32_t val; 560 561 if ((un->un_flags & LAN7500) && 562 MUE_WAIT_SET(un, MUE_PMT_CTL, MUE_PMT_CTL_READY, 0)) { 563 MUE_PRINTF(un, "not ready\n"); 564 return ETIMEDOUT; 565 } 566 567 MUE_SETBIT(un, MUE_HW_CFG, MUE_HW_CFG_LRST); 568 if (MUE_WAIT_CLR(un, MUE_HW_CFG, MUE_HW_CFG_LRST, 0)) { 569 MUE_PRINTF(un, "timed out\n"); 570 return ETIMEDOUT; 571 } 572 573 /* Respond to the IN token with a NAK. */ 574 if (un->un_flags & LAN7500) 575 MUE_SETBIT(un, MUE_HW_CFG, MUE_HW_CFG_BIR); 576 else 577 MUE_SETBIT(un, MUE_USB_CFG0, MUE_USB_CFG0_BIR); 578 579 if (un->un_flags & LAN7500) { 580 if (un->un_udev->ud_speed == USB_SPEED_HIGH) 581 val = MUE_7500_HS_RX_BUFSIZE / 582 MUE_HS_USB_PKT_SIZE; 583 else 584 val = MUE_7500_FS_RX_BUFSIZE / 585 MUE_FS_USB_PKT_SIZE; 586 mue_csr_write(un, MUE_7500_BURST_CAP, val); 587 mue_csr_write(un, MUE_7500_BULKIN_DELAY, 588 MUE_7500_DEFAULT_BULKIN_DELAY); 589 590 MUE_SETBIT(un, MUE_HW_CFG, MUE_HW_CFG_BCE | MUE_HW_CFG_MEF); 591 592 /* Set FIFO sizes. */ 593 val = (MUE_7500_MAX_RX_FIFO_SIZE - 512) / 512; 594 mue_csr_write(un, MUE_7500_FCT_RX_FIFO_END, val); 595 val = (MUE_7500_MAX_TX_FIFO_SIZE - 512) / 512; 596 mue_csr_write(un, MUE_7500_FCT_TX_FIFO_END, val); 597 } else { 598 /* Init LTM. */ 599 mue_init_ltm(un); 600 601 val = MUE_7800_RX_BUFSIZE; 602 switch (un->un_udev->ud_speed) { 603 case USB_SPEED_SUPER: 604 val /= MUE_SS_USB_PKT_SIZE; 605 break; 606 case USB_SPEED_HIGH: 607 val /= MUE_HS_USB_PKT_SIZE; 608 break; 609 default: 610 val /= MUE_FS_USB_PKT_SIZE; 611 break; 612 } 613 mue_csr_write(un, MUE_7800_BURST_CAP, val); 614 mue_csr_write(un, MUE_7800_BULKIN_DELAY, 615 MUE_7800_DEFAULT_BULKIN_DELAY); 616 617 MUE_SETBIT(un, MUE_HW_CFG, MUE_HW_CFG_MEF); 618 MUE_SETBIT(un, MUE_USB_CFG0, MUE_USB_CFG0_BCE); 619 620 /* 621 * Set FCL's RX and TX FIFO sizes: according to data sheet this 622 * is already the default value. But we initialize it to the 623 * same value anyways, as that's what the Linux driver does. 624 */ 625 val = (MUE_7800_MAX_RX_FIFO_SIZE - 512) / 512; 626 mue_csr_write(un, MUE_7800_FCT_RX_FIFO_END, val); 627 val = (MUE_7800_MAX_TX_FIFO_SIZE - 512) / 512; 628 mue_csr_write(un, MUE_7800_FCT_TX_FIFO_END, val); 629 } 630 631 /* Enabling interrupts. */ 632 mue_csr_write(un, MUE_INT_STATUS, ~0); 633 634 mue_csr_write(un, (un->un_flags & LAN7500) ? 635 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, 0); 636 mue_csr_write(un, MUE_FLOW, 0); 637 638 /* Reset PHY. */ 639 MUE_SETBIT(un, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST); 640 if (MUE_WAIT_CLR(un, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST, 0)) { 641 MUE_PRINTF(un, "PHY not ready\n"); 642 return ETIMEDOUT; 643 } 644 645 /* LAN7801 only has RGMII mode. */ 646 if (un->un_flags & LAN7801) 647 MUE_CLRBIT(un, MUE_MAC_CR, MUE_MAC_CR_GMII_EN); 648 649 if ((un->un_flags & (LAN7500 | LAN7800)) || 650 !mue_eeprom_present(un)) { 651 /* Allow MAC to detect speed and duplex from PHY. */ 652 MUE_SETBIT(un, MUE_MAC_CR, MUE_MAC_CR_AUTO_SPEED | 653 MUE_MAC_CR_AUTO_DUPLEX); 654 } 655 656 MUE_SETBIT(un, MUE_MAC_TX, MUE_MAC_TX_TXEN); 657 MUE_SETBIT(un, (un->un_flags & LAN7500) ? 658 MUE_7500_FCT_TX_CTL : MUE_7800_FCT_TX_CTL, MUE_FCT_TX_CTL_EN); 659 660 MUE_SETBIT(un, (un->un_flags & LAN7500) ? 661 MUE_7500_FCT_RX_CTL : MUE_7800_FCT_RX_CTL, MUE_FCT_RX_CTL_EN); 662 663 /* Set default GPIO/LED settings only if no EEPROM is detected. */ 664 if ((un->un_flags & LAN7500) && !mue_eeprom_present(un)) { 665 MUE_CLRBIT(un, MUE_LED_CFG, MUE_LED_CFG_LED10_FUN_SEL); 666 MUE_SETBIT(un, MUE_LED_CFG, 667 MUE_LED_CFG_LEDGPIO_EN | MUE_LED_CFG_LED2_FUN_SEL); 668 } 669 670 /* XXX We assume two LEDs at least when EEPROM is missing. */ 671 if (un->un_flags & LAN7800 && 672 !mue_eeprom_present(un)) 673 MUE_SETBIT(un, MUE_HW_CFG, 674 MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN); 675 676 return 0; 677 } 678 679 static void 680 mue_set_macaddr(struct usbnet *un) 681 { 682 struct ifnet * const ifp = usbnet_ifp(un); 683 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 684 uint32_t lo, hi; 685 686 lo = MUE_ENADDR_LO(enaddr); 687 hi = MUE_ENADDR_HI(enaddr); 688 689 mue_csr_write(un, MUE_RX_ADDRL, lo); 690 mue_csr_write(un, MUE_RX_ADDRH, hi); 691 } 692 693 static int 694 mue_get_macaddr(struct usbnet *un) 695 { 696 uint32_t low, high; 697 698 if (!(un->un_flags & LAN7500)) { 699 low = mue_csr_read(un, MUE_RX_ADDRL); 700 high = mue_csr_read(un, MUE_RX_ADDRH); 701 un->un_eaddr[5] = (uint8_t)((high >> 8) & 0xff); 702 un->un_eaddr[4] = (uint8_t)((high) & 0xff); 703 un->un_eaddr[3] = (uint8_t)((low >> 24) & 0xff); 704 un->un_eaddr[2] = (uint8_t)((low >> 16) & 0xff); 705 un->un_eaddr[1] = (uint8_t)((low >> 8) & 0xff); 706 un->un_eaddr[0] = (uint8_t)((low) & 0xff); 707 if (ETHER_IS_VALID(un->un_eaddr)) 708 return 0; 709 else 710 DPRINTF(un, "registers: %s\n", 711 ether_sprintf(un->un_eaddr)); 712 } 713 714 if (mue_eeprom_present(un) && !mue_read_eeprom(un, un->un_eaddr, 715 MUE_E2P_MAC_OFFSET, ETHER_ADDR_LEN)) { 716 if (ETHER_IS_VALID(un->un_eaddr)) 717 return 0; 718 else 719 DPRINTF(un, "EEPROM: %s\n", 720 ether_sprintf(un->un_eaddr)); 721 } 722 723 if (mue_read_otp(un, un->un_eaddr, MUE_OTP_MAC_OFFSET, 724 ETHER_ADDR_LEN) == 0) { 725 if (ETHER_IS_VALID(un->un_eaddr)) 726 return 0; 727 else 728 DPRINTF(un, "OTP: %s\n", 729 ether_sprintf(un->un_eaddr)); 730 } 731 732 /* 733 * Other MD methods. This should be tried only if other methods fail. 734 * Otherwise, MAC address for internal device can be assigned to 735 * external devices on Raspberry Pi, for example. 736 */ 737 if (ether_getaddr(un->un_dev, un->un_eaddr)) { 738 if (ETHER_IS_VALID(un->un_eaddr)) 739 return 0; 740 else 741 DPRINTF(un, "ether_getaddr: %s\n", 742 ether_sprintf(un->un_eaddr)); 743 } 744 745 return 1; 746 } 747 748 749 /* 750 * Probe for a Microchip chip. 751 */ 752 static int 753 mue_match(device_t parent, cfdata_t match, void *aux) 754 { 755 struct usb_attach_arg *uaa = aux; 756 757 return (MUE_LOOKUP(uaa) != NULL) ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 758 } 759 760 static void 761 mue_attach(device_t parent, device_t self, void *aux) 762 { 763 USBNET_MII_DECL_DEFAULT(unm); 764 struct usbnet * const un = device_private(self); 765 struct usb_attach_arg *uaa = aux; 766 struct usbd_device *dev = uaa->uaa_device; 767 usb_interface_descriptor_t *id; 768 usb_endpoint_descriptor_t *ed; 769 char *devinfop; 770 usbd_status err; 771 const char *descr; 772 uint32_t id_rev; 773 uint8_t i; 774 unsigned rx_list_cnt, tx_list_cnt; 775 unsigned rx_bufsz; 776 777 aprint_naive("\n"); 778 aprint_normal("\n"); 779 devinfop = usbd_devinfo_alloc(dev, 0); 780 aprint_normal_dev(self, "%s\n", devinfop); 781 usbd_devinfo_free(devinfop); 782 783 un->un_dev = self; 784 un->un_udev = dev; 785 un->un_sc = un; 786 un->un_ops = &mue_ops; 787 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 788 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 789 790 #define MUE_CONFIG_NO 1 791 err = usbd_set_config_no(dev, MUE_CONFIG_NO, 1); 792 if (err) { 793 aprint_error_dev(self, "failed to set configuration: %s\n", 794 usbd_errstr(err)); 795 return; 796 } 797 798 #define MUE_IFACE_IDX 0 799 err = usbd_device2interface_handle(dev, MUE_IFACE_IDX, &un->un_iface); 800 if (err) { 801 aprint_error_dev(self, "failed to get interface handle: %s\n", 802 usbd_errstr(err)); 803 return; 804 } 805 806 un->un_flags = MUE_LOOKUP(uaa)->mue_flags; 807 808 /* Decide on what our bufsize will be. */ 809 if (un->un_flags & LAN7500) { 810 rx_bufsz = (un->un_udev->ud_speed == USB_SPEED_HIGH) ? 811 MUE_7500_HS_RX_BUFSIZE : MUE_7500_FS_RX_BUFSIZE; 812 rx_list_cnt = 1; 813 tx_list_cnt = 1; 814 } else { 815 rx_bufsz = MUE_7800_RX_BUFSIZE; 816 rx_list_cnt = MUE_RX_LIST_CNT; 817 tx_list_cnt = MUE_TX_LIST_CNT; 818 } 819 820 un->un_rx_list_cnt = rx_list_cnt; 821 un->un_tx_list_cnt = tx_list_cnt; 822 un->un_rx_bufsz = rx_bufsz; 823 un->un_tx_bufsz = MUE_TX_BUFSIZE; 824 825 /* Find endpoints. */ 826 id = usbd_get_interface_descriptor(un->un_iface); 827 for (i = 0; i < id->bNumEndpoints; i++) { 828 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 829 if (ed == NULL) { 830 aprint_error_dev(self, "failed to get ep %hhd\n", i); 831 return; 832 } 833 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 834 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 835 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 836 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 837 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 838 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 839 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 840 UE_GET_XFERTYPE(ed->bmAttributes) == UE_INTERRUPT) { 841 un->un_ed[USBNET_ENDPT_INTR] = ed->bEndpointAddress; 842 } 843 } 844 if (un->un_ed[USBNET_ENDPT_RX] == 0 || 845 un->un_ed[USBNET_ENDPT_TX] == 0 || 846 un->un_ed[USBNET_ENDPT_INTR] == 0) { 847 aprint_error_dev(self, "failed to find endpoints\n"); 848 return; 849 } 850 851 /* Set these up now for mue_cmd(). */ 852 usbnet_attach(un); 853 854 un->un_phyno = 1; 855 856 if (mue_chip_init(un)) { 857 aprint_error_dev(self, "failed to initialize chip\n"); 858 return; 859 } 860 861 /* A Microchip chip was detected. Inform the world. */ 862 id_rev = mue_csr_read(un, MUE_ID_REV); 863 descr = (un->un_flags & LAN7500) ? "LAN7500" : "LAN7800"; 864 aprint_normal_dev(self, "%s id %#x rev %#x\n", descr, 865 (unsigned)__SHIFTOUT(id_rev, MUE_ID_REV_ID), 866 (unsigned)__SHIFTOUT(id_rev, MUE_ID_REV_REV)); 867 868 if (mue_get_macaddr(un)) { 869 aprint_error_dev(self, "failed to read MAC address\n"); 870 return; 871 } 872 873 struct ifnet *ifp = usbnet_ifp(un); 874 ifp->if_capabilities = IFCAP_TSOv4 | IFCAP_TSOv6 | 875 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 876 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 877 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 878 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx | 879 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx; 880 881 struct ethercom *ec = usbnet_ec(un); 882 ec->ec_capabilities = ETHERCAP_VLAN_MTU; 883 #if 0 /* XXX not yet */ 884 ec->ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU; 885 #endif 886 887 usbnet_attach_ifp(un, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 888 0, &unm); 889 } 890 891 static unsigned 892 mue_uno_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 893 { 894 struct ifnet * const ifp = usbnet_ifp(un); 895 struct mue_txbuf_hdr hdr; 896 uint32_t tx_cmd_a, tx_cmd_b; 897 int csum, len, rv; 898 bool tso, ipe, tpe; 899 900 if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - sizeof(hdr)) 901 return 0; 902 903 csum = m->m_pkthdr.csum_flags; 904 tso = csum & (M_CSUM_TSOv4 | M_CSUM_TSOv6); 905 ipe = csum & M_CSUM_IPv4; 906 tpe = csum & (M_CSUM_TCPv4 | M_CSUM_UDPv4 | 907 M_CSUM_TCPv6 | M_CSUM_UDPv6); 908 909 len = m->m_pkthdr.len; 910 if (__predict_false((!tso && len > (int)MUE_FRAME_LEN(ifp->if_mtu)) || 911 ( tso && len > MUE_TSO_FRAME_LEN))) { 912 MUE_PRINTF(un, "packet length %d\n too long", len); 913 return 0; 914 } 915 916 KASSERT((len & ~MUE_TX_CMD_A_LEN_MASK) == 0); 917 tx_cmd_a = len | MUE_TX_CMD_A_FCS; 918 919 if (tso) { 920 tx_cmd_a |= MUE_TX_CMD_A_LSO; 921 if (__predict_true(m->m_pkthdr.segsz > MUE_TX_MSS_MIN)) 922 tx_cmd_b = m->m_pkthdr.segsz; 923 else 924 tx_cmd_b = MUE_TX_MSS_MIN; 925 tx_cmd_b <<= MUE_TX_CMD_B_MSS_SHIFT; 926 KASSERT((tx_cmd_b & ~MUE_TX_CMD_B_MSS_MASK) == 0); 927 rv = mue_prepare_tso(un, m); 928 if (__predict_false(rv)) 929 return 0; 930 } else { 931 if (ipe) 932 tx_cmd_a |= MUE_TX_CMD_A_IPE; 933 if (tpe) 934 tx_cmd_a |= MUE_TX_CMD_A_TPE; 935 tx_cmd_b = 0; 936 } 937 938 hdr.tx_cmd_a = htole32(tx_cmd_a); 939 hdr.tx_cmd_b = htole32(tx_cmd_b); 940 941 memcpy(c->unc_buf, &hdr, sizeof(hdr)); 942 m_copydata(m, 0, len, c->unc_buf + sizeof(hdr)); 943 944 return len + sizeof(hdr); 945 } 946 947 /* 948 * L3 length field should be cleared. 949 */ 950 static int 951 mue_prepare_tso(struct usbnet *un, struct mbuf *m) 952 { 953 struct ether_header *eh; 954 struct ip *ip; 955 struct ip6_hdr *ip6; 956 uint16_t type, len = 0; 957 int off; 958 959 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 960 eh = mtod(m, struct ether_header *); 961 type = eh->ether_type; 962 } else 963 m_copydata(m, offsetof(struct ether_header, ether_type), 964 sizeof(type), &type); 965 switch (type = htons(type)) { 966 case ETHERTYPE_IP: 967 case ETHERTYPE_IPV6: 968 off = ETHER_HDR_LEN; 969 break; 970 case ETHERTYPE_VLAN: 971 off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 972 break; 973 default: 974 return EINVAL; 975 } 976 977 if (m->m_pkthdr.csum_flags & M_CSUM_TSOv4) { 978 if (__predict_true(m->m_len >= off + (int)sizeof(*ip))) { 979 ip = (void *)(mtod(m, char *) + off); 980 ip->ip_len = 0; 981 } else 982 m_copyback(m, off + offsetof(struct ip, ip_len), 983 sizeof(len), &len); 984 } else { 985 if (__predict_true(m->m_len >= off + (int)sizeof(*ip6))) { 986 ip6 = (void *)(mtod(m, char *) + off); 987 ip6->ip6_plen = 0; 988 } else 989 m_copyback(m, off + offsetof(struct ip6_hdr, ip6_plen), 990 sizeof(len), &len); 991 } 992 return 0; 993 } 994 995 static void 996 mue_uno_mcast(struct ifnet *ifp) 997 { 998 struct usbnet *un = ifp->if_softc; 999 struct ethercom *ec = usbnet_ec(un); 1000 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 1001 struct ether_multi *enm; 1002 struct ether_multistep step; 1003 uint32_t pfiltbl[MUE_NUM_ADDR_FILTX][2]; 1004 uint32_t hashtbl[MUE_DP_SEL_VHF_HASH_LEN]; 1005 uint32_t reg, rxfilt, h, hireg, loreg; 1006 size_t i; 1007 1008 if (usbnet_isdying(un)) 1009 return; 1010 1011 /* Clear perfect filter and hash tables. */ 1012 memset(pfiltbl, 0, sizeof(pfiltbl)); 1013 memset(hashtbl, 0, sizeof(hashtbl)); 1014 1015 reg = (un->un_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL; 1016 rxfilt = mue_csr_read(un, reg); 1017 rxfilt &= ~(MUE_RFE_CTL_PERFECT | MUE_RFE_CTL_MULTICAST_HASH | 1018 MUE_RFE_CTL_UNICAST | MUE_RFE_CTL_MULTICAST); 1019 1020 /* Always accept broadcast frames. */ 1021 rxfilt |= MUE_RFE_CTL_BROADCAST; 1022 1023 ETHER_LOCK(ec); 1024 if (usbnet_ispromisc(un)) { 1025 rxfilt |= MUE_RFE_CTL_UNICAST; 1026 allmulti: rxfilt |= MUE_RFE_CTL_MULTICAST; 1027 ec->ec_flags |= ETHER_F_ALLMULTI; 1028 if (usbnet_ispromisc(un)) 1029 DPRINTF(un, "promisc\n"); 1030 else 1031 DPRINTF(un, "allmulti\n"); 1032 } else { 1033 /* Now program new ones. */ 1034 pfiltbl[0][0] = MUE_ENADDR_HI(enaddr) | MUE_ADDR_FILTX_VALID; 1035 pfiltbl[0][1] = MUE_ENADDR_LO(enaddr); 1036 i = 1; 1037 ETHER_FIRST_MULTI(step, ec, enm); 1038 while (enm != NULL) { 1039 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1040 ETHER_ADDR_LEN)) { 1041 memset(pfiltbl, 0, sizeof(pfiltbl)); 1042 memset(hashtbl, 0, sizeof(hashtbl)); 1043 rxfilt &= ~MUE_RFE_CTL_MULTICAST_HASH; 1044 goto allmulti; 1045 } 1046 if (i < MUE_NUM_ADDR_FILTX) { 1047 /* Use perfect address table if possible. */ 1048 pfiltbl[i][0] = MUE_ENADDR_HI(enm->enm_addrlo) | 1049 MUE_ADDR_FILTX_VALID; 1050 pfiltbl[i][1] = MUE_ENADDR_LO(enm->enm_addrlo); 1051 } else { 1052 /* Otherwise, use hash table. */ 1053 rxfilt |= MUE_RFE_CTL_MULTICAST_HASH; 1054 h = (ether_crc32_be(enm->enm_addrlo, 1055 ETHER_ADDR_LEN) >> 23) & 0x1ff; 1056 hashtbl[h / 32] |= 1 << (h % 32); 1057 } 1058 i++; 1059 ETHER_NEXT_MULTI(step, enm); 1060 } 1061 ec->ec_flags &= ~ETHER_F_ALLMULTI; 1062 rxfilt |= MUE_RFE_CTL_PERFECT; 1063 if (rxfilt & MUE_RFE_CTL_MULTICAST_HASH) 1064 DPRINTF(un, "perfect filter and hash tables\n"); 1065 else 1066 DPRINTF(un, "perfect filter\n"); 1067 } 1068 ETHER_UNLOCK(ec); 1069 1070 for (i = 0; i < MUE_NUM_ADDR_FILTX; i++) { 1071 hireg = (un->un_flags & LAN7500) ? 1072 MUE_7500_ADDR_FILTX(i) : MUE_7800_ADDR_FILTX(i); 1073 loreg = hireg + 4; 1074 mue_csr_write(un, hireg, 0); 1075 mue_csr_write(un, loreg, pfiltbl[i][1]); 1076 mue_csr_write(un, hireg, pfiltbl[i][0]); 1077 } 1078 1079 mue_dataport_write(un, MUE_DP_SEL_VHF, MUE_DP_SEL_VHF_VLAN_LEN, 1080 MUE_DP_SEL_VHF_HASH_LEN, hashtbl); 1081 1082 mue_csr_write(un, reg, rxfilt); 1083 } 1084 1085 static void 1086 mue_sethwcsum_locked(struct usbnet *un) 1087 { 1088 struct ifnet * const ifp = usbnet_ifp(un); 1089 uint32_t reg, val; 1090 1091 KASSERT(IFNET_LOCKED(ifp)); 1092 1093 reg = (un->un_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL; 1094 val = mue_csr_read(un, reg); 1095 1096 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) { 1097 DPRINTF(un, "RX IPv4 hwcsum enabled\n"); 1098 val |= MUE_RFE_CTL_IP_COE; 1099 } else { 1100 DPRINTF(un, "RX IPv4 hwcsum disabled\n"); 1101 val &= ~MUE_RFE_CTL_IP_COE; 1102 } 1103 1104 if (ifp->if_capenable & 1105 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 1106 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) { 1107 DPRINTF(un, "RX L4 hwcsum enabled\n"); 1108 val |= MUE_RFE_CTL_TCPUDP_COE; 1109 } else { 1110 DPRINTF(un, "RX L4 hwcsum disabled\n"); 1111 val &= ~MUE_RFE_CTL_TCPUDP_COE; 1112 } 1113 1114 val &= ~MUE_RFE_CTL_VLAN_FILTER; 1115 1116 mue_csr_write(un, reg, val); 1117 } 1118 1119 static void 1120 mue_setmtu_locked(struct usbnet *un) 1121 { 1122 struct ifnet * const ifp = usbnet_ifp(un); 1123 uint32_t val; 1124 1125 KASSERT(IFNET_LOCKED(ifp)); 1126 1127 /* Set the maximum frame size. */ 1128 MUE_CLRBIT(un, MUE_MAC_RX, MUE_MAC_RX_RXEN); 1129 val = mue_csr_read(un, MUE_MAC_RX); 1130 val &= ~MUE_MAC_RX_MAX_SIZE_MASK; 1131 val |= MUE_MAC_RX_MAX_LEN(MUE_FRAME_LEN(ifp->if_mtu)); 1132 mue_csr_write(un, MUE_MAC_RX, val); 1133 MUE_SETBIT(un, MUE_MAC_RX, MUE_MAC_RX_RXEN); 1134 } 1135 1136 static void 1137 mue_uno_rx_loop(struct usbnet *un, struct usbnet_chain *c, uint32_t total_len) 1138 { 1139 struct ifnet * const ifp = usbnet_ifp(un); 1140 struct mue_rxbuf_hdr *hdrp; 1141 uint32_t rx_cmd_a; 1142 uint16_t pktlen; 1143 int csum; 1144 uint8_t *buf = c->unc_buf; 1145 bool v6; 1146 1147 KASSERTMSG(total_len <= un->un_rx_bufsz, "%u vs %u", 1148 total_len, un->un_rx_bufsz); 1149 1150 do { 1151 if (__predict_false(total_len < sizeof(*hdrp))) { 1152 MUE_PRINTF(un, "packet length %u too short\n", total_len); 1153 if_statinc(ifp, if_ierrors); 1154 return; 1155 } 1156 1157 hdrp = (struct mue_rxbuf_hdr *)buf; 1158 rx_cmd_a = le32toh(hdrp->rx_cmd_a); 1159 1160 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ERRORS)) { 1161 /* 1162 * We cannot use MUE_RX_CMD_A_RED bit here; 1163 * it is turned on in the cases of L3/L4 1164 * checksum errors which we handle below. 1165 */ 1166 MUE_PRINTF(un, "rx_cmd_a: %#x\n", rx_cmd_a); 1167 if_statinc(ifp, if_ierrors); 1168 return; 1169 } 1170 1171 pktlen = (uint16_t)(rx_cmd_a & MUE_RX_CMD_A_LEN_MASK); 1172 if (un->un_flags & LAN7500) 1173 pktlen -= 2; 1174 1175 if (__predict_false(pktlen < ETHER_HDR_LEN + ETHER_CRC_LEN || 1176 pktlen > MCLBYTES - ETHER_ALIGN || /* XXX */ 1177 pktlen + sizeof(*hdrp) > total_len)) { 1178 MUE_PRINTF(un, "invalid packet length %d\n", pktlen); 1179 if_statinc(ifp, if_ierrors); 1180 return; 1181 } 1182 1183 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ICSM)) { 1184 csum = 0; 1185 } else { 1186 v6 = rx_cmd_a & MUE_RX_CMD_A_IPV; 1187 switch (rx_cmd_a & MUE_RX_CMD_A_PID) { 1188 case MUE_RX_CMD_A_PID_TCP: 1189 csum = v6 ? 1190 M_CSUM_TCPv6 : M_CSUM_IPv4 | M_CSUM_TCPv4; 1191 break; 1192 case MUE_RX_CMD_A_PID_UDP: 1193 csum = v6 ? 1194 M_CSUM_UDPv6 : M_CSUM_IPv4 | M_CSUM_UDPv4; 1195 break; 1196 case MUE_RX_CMD_A_PID_IP: 1197 csum = v6 ? 0 : M_CSUM_IPv4; 1198 break; 1199 default: 1200 csum = 0; 1201 break; 1202 } 1203 csum &= ifp->if_csum_flags_rx; 1204 if (__predict_false((csum & M_CSUM_IPv4) && 1205 (rx_cmd_a & MUE_RX_CMD_A_ICE))) 1206 csum |= M_CSUM_IPv4_BAD; 1207 if (__predict_false((csum & ~M_CSUM_IPv4) && 1208 (rx_cmd_a & MUE_RX_CMD_A_TCE))) 1209 csum |= M_CSUM_TCP_UDP_BAD; 1210 } 1211 1212 usbnet_enqueue(un, buf + sizeof(*hdrp), pktlen, csum, 1213 0, M_HASFCS); 1214 1215 /* Attention: sizeof(hdr) = 10 */ 1216 pktlen = roundup(pktlen + sizeof(*hdrp), 4); 1217 if (pktlen > total_len) 1218 pktlen = total_len; 1219 total_len -= pktlen; 1220 buf += pktlen; 1221 } while (total_len > 0); 1222 } 1223 1224 static int 1225 mue_uno_init(struct ifnet *ifp) 1226 { 1227 struct usbnet * const un = ifp->if_softc; 1228 1229 mue_reset(un); 1230 1231 /* Set MAC address. */ 1232 mue_set_macaddr(un); 1233 1234 /* TCP/UDP checksum offload engines. */ 1235 mue_sethwcsum_locked(un); 1236 1237 /* Set MTU. */ 1238 mue_setmtu_locked(un); 1239 1240 return 0; 1241 } 1242 1243 static int 1244 mue_uno_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1245 { 1246 struct usbnet * const un = ifp->if_softc; 1247 1248 switch (cmd) { 1249 case SIOCSIFCAP: 1250 mue_sethwcsum_locked(un); 1251 break; 1252 case SIOCSIFMTU: 1253 mue_setmtu_locked(un); 1254 break; 1255 default: 1256 break; 1257 } 1258 1259 return 0; 1260 } 1261 1262 static void 1263 mue_reset(struct usbnet *un) 1264 { 1265 if (usbnet_isdying(un)) 1266 return; 1267 1268 /* Wait a little while for the chip to get its brains in order. */ 1269 usbd_delay_ms(un->un_udev, 1); 1270 1271 // mue_chip_init(un); /* XXX */ 1272 } 1273 1274 static void 1275 mue_uno_stop(struct ifnet *ifp, int disable) 1276 { 1277 struct usbnet * const un = ifp->if_softc; 1278 1279 mue_reset(un); 1280 } 1281 1282 #ifdef _MODULE 1283 #include "ioconf.c" 1284 #endif 1285 1286 USBNET_MODULE(mue) 1287
Indexes created Mon Oct 13 16:09:52 GMT 2025