| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 608 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
612 MULHS,
|
| TargetLowering.h | 2426 case ISD::MULHS:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 210 case ISD::MULHS:
|
| MipsSEISelLowering.cpp | 185 setOperationAction(ISD::MULHS, MVT::i32, Custom);
196 setOperationAction(ISD::MULHS, MVT::i64, Custom);
233 setOperationAction(ISD::MULHS, MVT::i32, Legal);
280 setOperationAction(ISD::MULHS, MVT::i64, Legal);
456 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
|
| /src/external/gpl3/gcc.old/dist/gcc/ |
| internal-fn.def | 174 DEF_INTERNAL_SIGNED_OPTAB_FN (MULHS, ECF_CONST | ECF_NOTHROW, first,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLoweringHVX.cpp | 116 setOperationAction(ISD::MULHS, T, Custom);
178 setOperationAction(ISD::MULHS, T, Custom);
1486 bool IsSigned = Op.getOpcode() == ISD::MULHS;
1515 // mulhs(Vs,Vt) =
2075 case ISD::MULHS:
2115 case ISD::MULHS:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86IntrinsicsInfo.h | 386 X86_INTRINSIC_DATA(avx2_pmulh_w, INTR_TYPE_2OP, ISD::MULHS, 0),
837 X86_INTRINSIC_DATA(avx512_pmulh_w_512, INTR_TYPE_2OP, ISD::MULHS, 0),
1057 X86_INTRINSIC_DATA(sse2_pmulh_w, INTR_TYPE_2OP, ISD::MULHS, 0),
|
| X86ISelLowering.cpp | 337 setOperationAction(ISD::MULHS, VT, Expand);
835 setOperationAction(ISD::MULHS, VT, Expand);
938 setOperationAction(ISD::MULHS, MVT::v4i32, Custom);
940 setOperationAction(ISD::MULHS, MVT::v16i8, Custom);
942 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
1342 setOperationAction(ISD::MULHS, MVT::v8i32, Custom);
1344 setOperationAction(ISD::MULHS, MVT::v16i16, HasInt256 ? Legal : Custom);
1346 setOperationAction(ISD::MULHS, MVT::v32i8, Custom);
1641 setOperationAction(ISD::MULHS, MVT::v16i32, Custom);
1642 setOperationAction(ISD::MULHS, MVT::v32i16, HasBWI ? Legal : Custom)
[all...] |
| /src/external/gpl3/gcc/dist/gcc/ |
| internal-fn.def | 273 DEF_INTERNAL_SIGNED_OPTAB_FN (MULHS, ECF_CONST | ECF_NOTHROW, first,
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 233 case ISD::MULHS: return "mulhs";
|
| LegalizeVectorOps.cpp | 366 case ISD::MULHS:
|
| LegalizeDAG.cpp | 3271 case ISD::MULHS: {
3288 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS;
3325 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
|
| TargetLowering.cpp | 5202 if (isOperationLegalOrCustom(ISD::MULHS, VT, IsAfterLegalization))
5203 return DAG.getNode(ISD::MULHS, dl, VT, X, Y);
6263 isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
6291 Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R);
8135 unsigned HiOp = Signed ? ISD::MULHS : ISD::MULHU;
8407 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCISelLowering.cpp | 110 setOperationAction(ISD::MULHS, MVT::i32, Legal);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 108 setOperationAction(ISD::MULHS, VT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 122 setOperationAction(ISD::MULHS, MVT::i8, Promote);
127 setOperationAction(ISD::MULHS, MVT::i16, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 393 setOperationAction(ISD::MULHS, MVT::i16, Expand);
397 setOperationAction(ISD::MULHS, MVT::i64, Expand);
426 setOperationAction(ISD::MULHS, VT, Expand);
555 setTargetDAGCombine(ISD::MULHS);
3981 case ISD::MULHS:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 115 setOperationAction(ISD::MULHS, MVT::i32, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 178 setOperationAction(ISD::MULHS, VT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 99 setOperationAction(ISD::MULHS, MVT::i32, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1658 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1681 setOperationAction(ISD::MULHS, MVT::i64, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 520 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1073 setOperationAction(ISD::MULHS, VT, Legal);
1076 setOperationAction(ISD::MULHS, VT, Expand);
1137 setOperationAction(ISD::MULHS, VT, Custom);
1291 setOperationAction(ISD::MULHS, MVT::v1i64, Custom);
1292 setOperationAction(ISD::MULHS, MVT::v2i64, Custom);
1492 setOperationAction(ISD::MULHS, VT, Custom);
3001 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
4622 case ISD::MULHS:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 86 ISD::MULHS, ISD::MULHU, ISD::UMUL_LOHI, ISD::SMUL_LOHI}) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelLowering.cpp | 173 setOperationAction(ISD::MULHS, IntVT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 128 {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU,
|
