| /src/external/gpl3/binutils/dist/gas/config/ |
| rl78-parse.h | 134 MULHU = 335, /* MULHU */
259 #define MULHU 335
|
| rl78-parse.y | 173 %token MACH MACHU MOV MOV1 MOVS MOVW MULH MULHU MULU
507 | MULHU { ISA_G14 ("MULHU"); }
1304 OPC(MULHU),
|
| rl78-parse.c | 320 MULHU = 335, /* MULHU */
445 #define MULHU 335
595 YYSYMBOL_MULHU = 80, /* MULHU */
1154 "MULHU", "MULU", "NOP", "NOT1", "ONEB", "ONEW", "OR", "OR1", "POP",
2751 { ISA_G14 ("MULHU"); }
2755 case 93: /* statement: MULHU $@12 */
4548 OPC(MULHU),
|
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| rl78-parse.h | 134 MULHU = 335, /* MULHU */
259 #define MULHU 335
|
| rl78-parse.y | 173 %token MACH MACHU MOV MOV1 MOVS MOVW MULH MULHU MULU
507 | MULHU { ISA_G14 ("MULHU"); }
1304 OPC(MULHU),
|
| rl78-parse.c | 320 MULHU = 335, /* MULHU */
445 #define MULHU 335
595 YYSYMBOL_MULHU = 80, /* MULHU */
1154 "MULHU", "MULU", "NOP", "NOT1", "ONEB", "ONEW", "OR", "OR1", "POP",
2751 { ISA_G14 ("MULHU"); }
2755 case 93: /* statement: MULHU $@12 */
4548 OPC(MULHU),
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 211 case ISD::MULHU: {
212 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
|
| MipsSEISelLowering.cpp | 186 setOperationAction(ISD::MULHU, MVT::i32, Custom);
197 setOperationAction(ISD::MULHU, MVT::i64, Custom);
234 setOperationAction(ISD::MULHU, MVT::i32, Legal);
281 setOperationAction(ISD::MULHU, MVT::i64, Legal);
457 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 608 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
611 MULHU,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 392 setOperationAction(ISD::MULHU, MVT::i16, Expand);
396 setOperationAction(ISD::MULHU, MVT::i64, Expand);
425 setOperationAction(ISD::MULHU, VT, Expand);
554 setTargetDAGCombine(ISD::MULHU);
1840 SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1);
1855 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2);
1869 SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2);
2011 DAG.getNode(ISD::MULHU, DL, VT, Z, NegYZ));
2014 SDValue Q = DAG.getNode(ISD::MULHU, DL, VT, X, Z);
3983 case ISD::MULHU
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86IntrinsicsInfo.h | 387 X86_INTRINSIC_DATA(avx2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
838 X86_INTRINSIC_DATA(avx512_pmulhu_w_512, INTR_TYPE_2OP, ISD::MULHU, 0),
1058 X86_INTRINSIC_DATA(sse2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 232 case ISD::MULHU: return "mulhu";
|
| LegalizeDAG.cpp | 3270 case ISD::MULHU:
3273 Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI;
3288 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS;
3326 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
|
| LegalizeVectorOps.cpp | 367 case ISD::MULHU:
|
| TargetLowering.cpp | 5360 if (isOperationLegalOrCustom(ISD::MULHU, VT, IsAfterLegalization))
5361 return DAG.getNode(ISD::MULHU, dl, VT, X, Y);
5367 return SDValue(); // No mulhu or equivalent
5382 // MULHU to act as a SRL-by-1 for NPQ, else multiply by zero.
6265 isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
6291 Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R);
8135 unsigned HiOp = Signed ? ISD::MULHS : ISD::MULHU;
8406 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCISelLowering.cpp | 111 setOperationAction(ISD::MULHU, MVT::i32, Legal);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 107 setOperationAction(ISD::MULHU, VT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLoweringHVX.cpp | 117 setOperationAction(ISD::MULHU, T, Custom);
179 setOperationAction(ISD::MULHU, T, Custom);
2076 case ISD::MULHU:
2116 case ISD::MULHU: return LowerHvxMulh(Op, DAG);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 123 setOperationAction(ISD::MULHU, MVT::i8, Promote);
128 setOperationAction(ISD::MULHU, MVT::i16, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 114 setOperationAction(ISD::MULHU, MVT::i32, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 1010 if (TLI->isOperationLegalOrCustom(ISD::MULHU, VT)) {
|
| AArch64ISelLowering.cpp | 519 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1074 setOperationAction(ISD::MULHU, VT, Legal);
1077 setOperationAction(ISD::MULHU, VT, Expand);
1138 setOperationAction(ISD::MULHU, VT, Custom);
1293 setOperationAction(ISD::MULHU, MVT::v1i64, Custom);
1294 setOperationAction(ISD::MULHU, MVT::v2i64, Custom);
1493 setOperationAction(ISD::MULHU, VT, Custom);
3010 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
4625 case ISD::MULHU:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 179 setOperationAction(ISD::MULHU, VT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 100 setOperationAction(ISD::MULHU, MVT::i32, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1657 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1680 setOperationAction(ISD::MULHU, MVT::i64, Expand);
|
