| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyDebugValueManager.h | 11 /// manager for DebugValues associated with the specific MachineInstr.
22 class MachineInstr;
25 SmallVector<MachineInstr *, 2> DbgValues;
29 WebAssemblyDebugValueManager(MachineInstr *Instr);
31 void move(MachineInstr *Insert);
33 void clone(MachineInstr *Insert, unsigned NewReg);
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| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| CombinerHelper.h | 32 class MachineInstr;
43 MachineInstr *MI;
64 MachineInstr *Logic;
65 MachineInstr *Shift2;
124 bool tryCombineCopy(MachineInstr &MI);
125 bool matchCombineCopy(MachineInstr &MI);
126 void applyCombineCopy(MachineInstr &MI);
130 bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI);
138 bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI)
[all...] |
| LegalizerHelper.h | 81 LegalizeResult legalizeInstrStep(MachineInstr &MI);
84 LegalizeResult libcall(MachineInstr &MI);
88 LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
93 LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
96 LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
100 LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
104 LegalizeResult fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
109 LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
123 void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx,
129 void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx)
[all...] |
| LostDebugLocObserver.h | 22 SmallPtrSet<MachineInstr *, 4> PotentialMIsForDebugLocs;
40 void createdInstr(MachineInstr &MI) override;
41 void erasingInstr(MachineInstr &MI) override;
42 void changingInstr(MachineInstr &MI) override;
43 void changedInstr(MachineInstr &MI) override;
|
| GISelWorkList.h | 17 class MachineInstr;
29 SmallVector<MachineInstr *, N> Worklist;
30 DenseMap<MachineInstr *, unsigned> WorklistMap;
51 void deferred_insert(MachineInstr *I) {
75 void insert(MachineInstr *I) {
82 void remove(const MachineInstr *I) {
99 MachineInstr *pop_back_val() {
101 MachineInstr *I;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| GCNHazardRecognizer.h | 25 class MachineInstr;
35 typedef function_ref<bool(const MachineInstr &)> IsHazardFn;
44 MachineInstr *CurrCycleInstr;
45 std::list<MachineInstr*> EmittedInstrs;
63 void addClauseInst(const MachineInstr &MI);
65 // Advance over a MachineInstr bundle. Look for hazards in the bundled
73 int checkSoftClauseHazards(MachineInstr *SMEM);
74 int checkSMRDHazards(MachineInstr *SMRD);
75 int checkVMEMHazards(MachineInstr* VMEM);
76 int checkDPPHazards(MachineInstr *DPP)
[all...] |
| AMDGPULegalizerInfo.h | 39 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
45 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
47 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
53 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
59 bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
60 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI
[all...] |
| AMDGPUInstructionSelector.h | 42 class MachineInstr;
62 bool select(MachineInstr &I) override;
71 const MachineInstr &GEP;
75 GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
80 bool isInstrUniform(const MachineInstr &MI) const;
88 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
94 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
95 bool selectCOPY(MachineInstr &I) const;
96 bool selectPHI(MachineInstr &I) const;
97 bool selectG_TRUNC(MachineInstr &I) const
[all...] |
| AMDGPURegisterBankInfo.h | 52 MachineInstr &MI,
63 MachineInstr &MI,
66 bool executeInWaterfallLoop(MachineInstr &MI,
70 void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI,
72 bool applyMappingDynStackAlloc(MachineInstr &MI,
75 bool applyMappingLoad(MachineInstr &MI,
79 applyMappingImage(MachineInstr &MI,
93 MachineInstr *selectStoreIntrinsic(MachineIRBuilder &B,
94 MachineInstr &MI) const;
103 getInstrMappingForLoad(const MachineInstr &MI) const
[all...] |
| R600InstrInfo.h | 35 class MachineInstr;
45 ExtractSrcs(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PV,
92 bool canBeConsideredALU(const MachineInstr &MI) const;
95 bool isTransOnly(const MachineInstr &MI) const;
97 bool isVectorOnly(const MachineInstr &MI) const;
101 bool usesVertexCache(const MachineInstr &MI) const;
103 bool usesTextureCache(const MachineInstr &MI) const;
106 bool usesAddressRegister(MachineInstr &MI) const;
107 bool definesAddressRegister(MachineInstr &MI) const;
108 bool readsLDSSrcReg(const MachineInstr &MI) const
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.h | 34 class MachineInstr;
57 unsigned isLoadFromStackSlot(const MachineInstr &MI,
65 unsigned isStoreToStackSlot(const MachineInstr &MI,
72 const MachineInstr &MI,
79 const MachineInstr &MI,
204 bool expandPostRAPseudo(MachineInstr &MI) const override;
208 const MachineInstr &LdSt,
223 bool isPredicated(const MachineInstr &MI) const override;
226 bool isPostIncrement(const MachineInstr &MI) const override;
230 bool PredicateInstruction(MachineInstr &MI
[all...] |
| HexagonVLIWPacketizer.h | 23 class MachineInstr;
29 std::vector<MachineInstr *> OldPacketMIs;
54 std::vector<MachineInstr*> IgnoreDepMIs;
86 bool ignorePseudoInstruction(const MachineInstr &MI,
91 bool isSoloInstruction(const MachineInstr &MI) override;
102 MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
105 bool shouldAddToPacket(const MachineInstr &MI) override;
116 bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
118 bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
121 bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| MachineStableHash.h | 9 // Stable hashing for MachineInstr and MachineOperand. Useful or getting a
20 class MachineInstr;
24 stable_hash stableHashValue(const MachineInstr &MI, bool HashVRegs = false,
|
| ReachingDefAnalysis.h | 34 class MachineInstr;
94 DenseMap<MachineInstr *, int> InstIds;
107 using InstSet = SmallPtrSetImpl<MachineInstr*>;
142 int getReachingDef(MachineInstr *MI, MCRegister PhysReg) const;
145 bool hasSameReachingDef(MachineInstr *A, MachineInstr *B,
150 bool isReachingDefLiveOut(MachineInstr *MI, MCRegister PhysReg) const;
154 MachineInstr *getLocalLiveOutMIDef(MachineBasicBlock *MBB,
157 /// If a single MachineInstr creates the reaching definition, then return it.
159 MachineInstr *getUniqueReachingMIDef(MachineInstr *MI
[all...] |
| MacroFusion.h | 22 class MachineInstr;
32 const MachineInstr *FirstMI,
33 const MachineInstr &SecondMI)>;
|
| TargetInstrInfo.h | 24 #include "llvm/CodeGen/MachineInstr.h"
124 bool isTriviallyReMaterializable(const MachineInstr &MI,
140 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
160 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
183 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
196 bool isFrameInstr(const MachineInstr &I) const {
202 bool isFrameSetup(const MachineInstr &I) const {
214 int64_t getFrameSize(const MachineInstr &I) const {
223 int64_t getFrameTotalSize(const MachineInstr &I) const
[all...] |
| TargetSchedule.h | 27 class MachineInstr;
60 const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
102 bool mustBeginGroup(const MachineInstr *MI,
105 bool mustEndGroup(const MachineInstr *MI,
109 unsigned getNumMicroOps(const MachineInstr *MI,
174 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
175 const MachineInstr *UseMI, unsigned UseOperIdx)
189 unsigned computeInstrLatency(const MachineInstr *MI,
198 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
199 const MachineInstr *DepMI) const
[all...] |
| AntiDepBreaker.h | 19 #include "llvm/CodeGen/MachineInstr.h"
35 std::vector<std::pair<MachineInstr *, MachineInstr *>>;
52 virtual void Observe(MachineInstr &MI, unsigned Count,
60 void UpdateDbgValue(MachineInstr &MI, unsigned OldReg, unsigned NewReg) {
69 void UpdateDbgValues(const DbgValueVector &DbgValues, MachineInstr *ParentMI,
73 MachineInstr *PrevDbgMI = nullptr;
75 MachineInstr *PrevMI = DV.second;
77 MachineInstr *DbgMI = DV.first;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsRegisterBankInfo.h | 39 getInstrMapping(const MachineInstr &MI) const override;
50 void setRegBank(MachineInstr &MI, MachineRegisterInfo &MRI) const;
125 SmallVector<MachineInstr *, 2> DefUses;
126 SmallVector<MachineInstr *, 2> UseDefs;
136 MachineInstr *skipCopiesOutgoing(MachineInstr *MI) const;
143 MachineInstr *skipCopiesIncoming(MachineInstr *MI) const;
146 AmbiguousRegDefUseContainer(const MachineInstr *MI);
147 SmallVectorImpl<MachineInstr *> &getDefUses() { return DefUses;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64LegalizerInfo.h | 32 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
35 MachineInstr &MI) const override;
38 bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
40 bool legalizeLoadStore(MachineInstr &MI, MachineRegisterInfo &MRI,
43 bool legalizeShlAshrLshr(MachineInstr &MI, MachineRegisterInfo &MRI,
47 bool legalizeSmallCMGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
50 bool legalizeVectorTrunc(MachineInstr &MI, LegalizerHelper &Helper) const;
51 bool legalizeBitfieldExtract(MachineInstr &MI, MachineRegisterInfo &MRI,
53 bool legalizeRotate(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeCTPOP(MachineInstr &MI, MachineRegisterInfo &MRI
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 33 AC_EVEX_2_VEX = MachineInstr::TAsmComments
47 CondCode getCondFromBranch(const MachineInstr &MI);
50 CondCode getCondFromSETCC(const MachineInstr &MI);
53 CondCode getCondFromCMov(const MachineInstr &MI);
110 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
123 inline static bool isMem(const MachineInstr &MI, unsigned Op) {
139 SmallVectorImpl<MachineInstr *> &CondBranches,
153 int64_t getFrameAdjustment(const MachineInstr &I) const {
162 void setFrameAdjustment(MachineInstr &I, int64_t V) const {
173 int getSPAdjust(const MachineInstr &MI) const override
[all...] |
| X86AsmPrinter.h | 82 void LowerSTACKMAP(const MachineInstr &MI);
83 void LowerPATCHPOINT(const MachineInstr &MI, X86MCInstLower &MCIL);
84 void LowerSTATEPOINT(const MachineInstr &MI, X86MCInstLower &MCIL);
85 void LowerFAULTING_OP(const MachineInstr &MI, X86MCInstLower &MCIL);
86 void LowerPATCHABLE_OP(const MachineInstr &MI, X86MCInstLower &MCIL);
88 void LowerTlsAddr(X86MCInstLower &MCInstLowering, const MachineInstr &MI);
91 void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
93 void LowerPATCHABLE_RET(const MachineInstr &MI, X86MCInstLower &MCIL);
94 void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
95 void LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI, X86MCInstLower &MCIL)
[all...] |
| X86FastTileConfig.cpp | 27 #include "llvm/CodeGen/MachineInstr.h"
48 MachineInstr *getTileConfigPoint();
55 bool isTileLoad(MachineInstr &MI);
56 bool isTileStore(MachineInstr &MI);
57 bool isAMXInstr(MachineInstr &MI);
58 void getTileStoreShape(MachineInstr &MI,
61 MachineInstr *getKeyAMXInstr(MachineInstr *MI);
62 void getTileShapesCfg(MachineInstr *MI,
64 void getShapeCfgInstrs(MachineInstr *MI
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMMacroFusion.cpp | 22 static bool isAESPair(const MachineInstr *FirstMI,
23 const MachineInstr &SecondMI) {
38 static bool isLiteralsPair(const MachineInstr *FirstMI,
39 const MachineInstr &SecondMI) {
53 const MachineInstr *FirstMI,
54 const MachineInstr &SecondMI) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.h | 196 SmallVectorImpl<MachineInstr *> &NewMIs) const;
200 SmallVectorImpl<MachineInstr *> &NewMIs) const;
204 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
205 unsigned OpNoForForwarding, MachineInstr **KilledDef) const;
208 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
212 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
214 MachineInstr &DefMI) const;
217 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III
[all...] |
