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    Searched refs:MaskLo (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorTypes.cpp 1745 SDValue MaskLo, MaskHi;
1747 SplitVecRes_SETCC(Mask.getNode(), MaskLo, MaskHi);
1750 GetSplitVector(Mask, MaskLo, MaskHi);
1752 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1772 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, Offset, MaskLo, PassThruLo, LoMemVT,
1782 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, dl, LoMemVT, DAG,
1830 SDValue MaskLo, MaskHi;
1832 SplitVecRes_SETCC(Mask.getNode(), MaskLo, MaskHi);
1835 GetSplitVector(Mask, MaskLo, MaskHi);
1837 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl)
    [all...]
TargetLowering.cpp 1861 APInt MaskLo = DemandedBits.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
1866 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownLo, TLO, Depth + 1))
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.cpp 2550 Register MaskLo = MRI->createVirtualRegister(&RegRC);
2553 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), MaskLo)
2557 .addReg(MaskLo);
AMDGPURegisterBankInfo.cpp 2557 Register MaskLo = B.buildConstant(S32, 0xffff).getReg(0);
2558 MRI.setRegBank(MaskLo, *BankLo);
2566 ZextLo = B.buildAnd(S32, Lo, MaskLo).getReg(0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 23261 static const int MaskLo[] = { 0, 0, 2, 2 };
23263 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
    [all...]

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