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    Searched refs:MaskReg (Results 1 - 10 of 10) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVExpandAtomicPseudoInsts.cpp 259 Register MaskReg, Register ScratchReg) {
261 assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique");
262 assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique");
272 .addReg(MaskReg);
287 Register MaskReg = MI.getOperand(4).getReg();
329 insertMaskedMerge(TII, DL, LoopMBB, ScratchReg, DestReg, ScratchReg, MaskReg,
427 Register MaskReg = MI.getOperand(5).getReg();
443 .addReg(MaskReg);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
MipsNaClELFStreamer.cpp 101 void emitMask(unsigned AddrReg, unsigned MaskReg,
107 MaskInst.addOperand(MCOperand::createReg(MaskReg));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64InstrInfo.h 355 bool optimizePTestInstr(MachineInstr *PTest, unsigned MaskReg,
AArch64InstrInfo.cpp 1306 MachineInstr *PTest, unsigned MaskReg, unsigned PredReg,
1308 auto *Mask = MRI->getUniqueVRegDef(MaskReg);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
MachineIRBuilder.cpp 213 Register MaskReg = getMRI()->createGenericVirtualRegister(MaskTy);
214 buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits));
215 return buildPtrMask(Res, Op0, MaskReg);
LegalizerHelper.cpp 6806 Register MaskReg = MI.getOperand(1).getReg();
6810 LLT MaskTy = MRI.getType(MaskReg);
6818 Register MaskElt = MaskReg;
6833 auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg);
6834 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.cpp 2488 Register MaskReg = I.getOperand(2).getReg();
2490 LLT MaskTy = MRI->getType(MaskReg);
2494 const RegisterBank *MaskRB = RBI.getRegBank(MaskReg, *MRI, TRI);
2512 !RBI.constrainGenericRegister(MaskReg, *MaskRC, *MRI))
2523 .addReg(MaskReg);
2541 APInt MaskOnes = KnownBits->getKnownOnes(MaskReg).zextOrSelf(64);
2554 .addReg(MaskReg, 0, AMDGPU::sub0);
2568 .addReg(MaskReg, 0, AMDGPU::sub1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 11221 Register MaskReg = RegInfo.createVirtualRegister(GPRC);
11297 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
11311 .addReg(MaskReg);
11312 BuildMI(BB, dl, TII->get(PPC::AND), Tmp3Reg).addReg(TmpReg).addReg(MaskReg);
11319 .addReg(MaskReg);
12230 Register MaskReg = RegInfo.createVirtualRegister(GPRC);
12316 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
12321 .addReg(MaskReg);
12324 .addReg(MaskReg);
12332 .addReg(MaskReg);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 2798 Register MaskReg = I.getOperand(2).getReg();
2799 Optional<int64_t> MaskVal = getConstantVRegSExtVal(MaskReg, MRI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrInfo.cpp 3371 // SrcReg(MaskReg) -> DestReg(GR64)
3372 // SrcReg(MaskReg) -> DestReg(GR32)
3384 // SrcReg(GR64) -> DestReg(MaskReg)
3385 // SrcReg(GR32) -> DestReg(MaskReg)
4763 Register MaskReg = MIB.getReg(1);
4771 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)

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