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    Searched refs:MatchInfo (Results 1 - 10 of 10) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
CombinerHelper.h 143 bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
144 void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
149 bool matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo);
150 void applyCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo);
156 bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
157 bool applySextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
241 bool matchPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo);
242 bool applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo);
245 bool matchShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo);
246 bool applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo);
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUPreLegalizerCombiner.cpp 51 ClampI64ToI16MatchInfo &MatchInfo);
54 const ClampI64ToI16MatchInfo &MatchInfo);
59 ClampI64ToI16MatchInfo &MatchInfo) {
73 auto IsApplicableForCombine = [&MatchInfo]() -> bool {
74 const auto Cmp1 = MatchInfo.Cmp1;
75 const auto Cmp2 = MatchInfo.Cmp2;
93 m_GSMin(m_Reg(Base), m_ICst(MatchInfo.Cmp1)))) {
95 m_GSMax(m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2)))) {
101 m_GSMax(m_Reg(Base), m_ICst(MatchInfo.Cmp1))))
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AMDGPURegBankCombiner.cpp 64 bool matchIntMinMaxToMed3(MachineInstr &MI, Med3MatchInfo &MatchInfo);
65 void applyMed3(MachineInstr &MI, Med3MatchInfo &MatchInfo);
109 MachineInstr &MI, Med3MatchInfo &MatchInfo) {
130 MatchInfo = {OpcodeTriple.Med, Val, K0, K1};
135 Med3MatchInfo &MatchInfo) {
137 B.buildInstr(MatchInfo.Opc, {MI.getOperand(0)},
138 {MatchInfo.Val0, MatchInfo.Val1, MatchInfo.Val2}, MI.getFlags());
AMDGPUPostLegalizerCombiner.cpp 66 bool matchCvtF32UByteN(MachineInstr &MI, CvtF32UByteMatchInfo &MatchInfo);
68 const CvtF32UByteMatchInfo &MatchInfo);
205 MachineInstr &MI, CvtF32UByteMatchInfo &MatchInfo) {
223 MatchInfo.CvtVal = Src0;
224 MatchInfo.ShiftOffset = ShiftOffset;
233 MachineInstr &MI, const CvtF32UByteMatchInfo &MatchInfo) {
235 unsigned NewOpc = AMDGPU::G_AMDGPU_CVT_F32_UBYTE0 + MatchInfo.ShiftOffset / 8;
238 Register CvtSrc = MatchInfo.CvtVal;
239 LLT SrcTy = MRI.getType(MatchInfo.CvtVal);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostLegalizerLowering.cpp 219 ShuffleVectorPseudo &MatchInfo) {
235 MatchInfo = ShuffleVectorPseudo(AArch64::G_REV64, Dst, {Src});
248 ShuffleVectorPseudo &MatchInfo) {
259 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2});
267 /// \param [out] MatchInfo - Either G_UZP1 or G_UZP2 on success.
269 ShuffleVectorPseudo &MatchInfo) {
280 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2});
285 ShuffleVectorPseudo &MatchInfo) {
296 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2});
303 ShuffleVectorPseudo &MatchInfo) {
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AArch64PostLegalizerCombiner.cpp 52 std::tuple<unsigned, LLT, Register> &MatchInfo) {
85 std::get<0>(MatchInfo) = TargetOpcode::G_FADD;
86 std::get<1>(MatchInfo) = DstTy;
87 std::get<2>(MatchInfo) = Other->getOperand(0).getReg();
95 std::tuple<unsigned, LLT, Register> &MatchInfo) {
96 unsigned Opc = std::get<0>(MatchInfo);
99 LLT Ty = std::get<1>(MatchInfo);
100 Register Src = std::get<2>(MatchInfo);
246 std::function<void(MachineIRBuilder &)> &MatchInfo) {
263 MatchInfo = [=](MachineIRBuilder &B)
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AArch64PreLegalizerCombiner.cpp 65 GISelKnownBits *KB, Register &MatchInfo) {
89 MatchInfo = WideReg;
117 std::pair<uint64_t, uint64_t> &MatchInfo) {
178 MatchInfo = std::make_pair(NewOffset, MinOffset);
185 std::pair<uint64_t, uint64_t> &MatchInfo) {
207 std::tie(Offset, MinOffset) = MatchInfo;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CombinerHelper.cpp 691 MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo) {
721 MatchInfo = std::make_tuple(LoadDef->getOperand(0).getReg(), NewSizeBits);
726 MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo) {
730 std::tie(LoadReg, ScalarSizeBits) = MatchInfo;
881 IndexedLoadStoreMatchInfo MatchInfo;
882 if (matchCombineIndexedLoadStore(MI, MatchInfo)) {
883 applyCombineIndexedLoadStore(MI, MatchInfo);
889 bool CombinerHelper::matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo) {
900 MatchInfo.IsPre = findPreIndexCandidate(MI, MatchInfo.Addr, MatchInfo.Base
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  /src/external/apache2/llvm/dist/llvm/lib/FileCheck/
FileCheck.cpp 1289 SmallVector<StringRef, 4> MatchInfo;
1293 if (!Regex(RegExToMatch, Flags).match(Buffer, &MatchInfo))
1297 assert(!MatchInfo.empty() && "Didn't get any match");
1298 StringRef FullMatch = MatchInfo[0];
1302 assert(VariableDef.second < MatchInfo.size() && "Internal paren error");
1304 MatchInfo[VariableDef.second];
1320 assert(CaptureParenGroup < MatchInfo.size() && "Internal paren error");
1324 StringRef MatchedValue = MatchInfo[CaptureParenGroup];
  /src/external/public-domain/sqlite/dist/
sqlite3.c     [all...]

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