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    Searched refs:MaxVGPRs (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUPromoteAlloca.cpp 74 unsigned MaxVGPRs;
178 MaxVGPRs = ST.getMaxNumVGPRs(ST.getWavesPerEU(F).first);
180 MaxVGPRs = 128;
408 unsigned MaxVGPRs) {
425 : (MaxVGPRs * 32);
429 << MaxVGPRs << " registers available\n");
860 if (tryPromoteAllocaToVector(&I, DL, MaxVGPRs))
1080 bool handlePromoteAllocaToVector(AllocaInst &I, unsigned MaxVGPRs) {
1089 return tryPromoteAllocaToVector(&I, Mod->getDataLayout(), MaxVGPRs);
1100 unsigned MaxVGPRs;
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SIFormMemoryClauses.cpp 76 unsigned MaxVGPRs;
209 MaxPressure.getVGPRNum(ST->hasGFX90AInsts()) <= MaxVGPRs / 2 &&
275 MaxVGPRs = TRI->getAllocatableSet(MF, &AMDGPU::VGPR_32RegClass).count();
GCNSchedStrategy.cpp 388 unsigned MaxVGPRs = ST.getMaxNumVGPRs(MF);
390 if (PressureAfter.getVGPRNum(false) > MaxVGPRs ||
391 PressureAfter.getAGPRNum() > MaxVGPRs ||
AMDGPUTargetTransformInfo.h 74 unsigned MaxVGPRs;
AMDGPUTargetTransformInfo.cpp 289 MaxVGPRs(ST->getMaxNumVGPRs(
301 return MaxVGPRs;
SIInstrInfo.cpp 555 unsigned MaxVGPRs = RI.getRegPressureLimit(&AMDGPU::VGPR_32RegClass,
572 if (!Tmp2 || RI.getHWRegIndex(Tmp2) >= MaxVGPRs)

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