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    Searched refs:MemMI (Results 1 - 2 of 2) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64LoadStoreOptimizer.cpp 175 bool isMatchingUpdateInsn(MachineInstr &MemMI, MachineInstr &MI,
1833 bool AArch64LoadStoreOpt::isMatchingUpdateInsn(MachineInstr &MemMI,
1862 getPrePostIndexedMemOpInfo(MemMI, Scale, MinOffset, MaxOffset);
1888 MachineInstr &MemMI = *I;
1891 Register BaseReg = getLdStBaseOp(MemMI).getReg();
1892 int MIUnscaledOffset = getLdStOffsetOp(MemMI).getImm() * TII->getMemScale(MemMI);
1906 if (!isTagStore(MemMI) && MemMI.getOpcode() != AArch64::STGPi) {
1907 bool IsPairedInsn = isPairedLdSt(MemMI);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp 202 MachineInstr *MemMI = nullptr;
276 MemMI =
282 MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
288 NewMIs.push_back(MemMI);
292 MemMI =
298 MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
307 NewMIs.push_back(MemMI);
319 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;

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