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    Searched refs:MemVT (Results 1 - 25 of 39) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
SelectionDAG.h 1106 SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT,
1112 SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain,
1117 SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, EVT VT,
1122 SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
1132 EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment,
1139 EVT MemVT, MachinePointerInfo PtrInfo, MaybeAlign Alignment = None,
1144 return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, PtrInfo,
1145 Alignment.getValueOr(getEVTAlign(MemVT)), Flags,
1150 ArrayRef<SDValue> Ops, EVT MemVT,
1193 SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT,
    [all...]
SelectionDAGNodes.h 1257 EVT memvt, MachineMemOperand *MMO);
1397 EVT MemVT, MachineMemOperand *MMO)
1398 : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
2221 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
2223 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2255 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
2257 : LSBaseSDNode(ISD::LOAD, Order, dl, VTs, AM, MemVT, MMO) {
2283 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
2285 : LSBaseSDNode(ISD::STORE, Order, dl, VTs, AM, MemVT, MMO) {
2316 ISD::MemIndexedMode AM, EVT MemVT,
    [all...]
TargetLowering.h 574 virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
583 virtual bool mergeStoresAfterLegalization(EVT MemVT) const {
587 /// Returns if it's reasonable to merge stores to MemVT size.
588 virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
984 EVT memVT; // memory VT
991 // (taken from memVT if zero)
1221 EVT MemVT) const {
1222 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1224 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1232 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const
    [all...]
BasicTTIImpl.h 1100 EVT MemVT = getTLI()->getValueType(DL, Src);
1102 LA = getTLI()->getTruncStoreAction(LT.second, MemVT);
1104 LA = getTLI()->getLoadExtAction(ISD::EXTLOAD, LT.second, MemVT);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp 1074 EVT MemVT = Store->getMemoryVT();
1107 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1148 EVT MemVT = StoreNode->getMemoryVT();
1165 MemVT, StoreNode->getAlignment(),
1174 if (Alignment < MemVT.getStoreSize() &&
1175 !allowsMisalignedMemoryAccesses(MemVT, AS, Alignment,
1190 if (MemVT == MVT::i8) {
1193 assert(MemVT == MVT::i16);
1221 Op->getVTList(), Args, MemVT,
1240 if (MemVT.bitsLT(MVT::i32)
    [all...]
R600ISelLowering.h 49 bool canMergeStoresTo(unsigned AS, EVT MemVT,
SIISelLowering.h 50 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
116 ArrayRef<SDValue> Ops, EVT MemVT,
130 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
160 EVT MemVT,
271 bool canMergeStoresTo(unsigned AS, EVT MemVT,
AMDGPUISelLowering.cpp 854 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
1053 EVT MemVT = ArgVT;
1062 MemVT = RegisterVT;
1064 MemVT = ArgVT;
1072 MemVT = RegisterVT;
1077 MemVT = ArgVT.getScalarType();
1080 MemVT = RegisterVT;
1085 MemVT = EVT::getIntegerVT(State.getContext(), MemoryBits);
1094 MemVT = EVT::getVectorVT(State.getContext(), ScalarVT, NumElements);
1101 if (MemVT.isVector() && MemVT.getVectorNumElements() == 1
    [all...]
SIISelLowering.cpp 1007 // correct memVT.
1056 Info.memVT = memVTFromImageReturn(CI.getType(), DMaskLanes);
1058 Info.memVT = EVT::getEVT(CI.getType());
1070 Info.memVT = memVTFromImageData(DataTy, DMaskLanes);
1072 Info.memVT = EVT::getEVT(DataTy);
1079 Info.memVT = MVT::getVT(CI.getArgOperand(0)->getType());
1099 Info.memVT = MVT::getVT(CI.getType());
1114 Info.memVT = MVT::getVT(CI.getOperand(0)->getType());
1129 Info.memVT = MVT::getVT(CI.getType());
1142 Info.memVT = MVT::getVT(CI.getType())
    [all...]
AMDGPUISelLowering.h 185 bool storeOfVectorConstantIsCheap(EVT MemVT,
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 681 EVT &MemVT, unsigned ShAmt = 0);
701 EVT MemVT, unsigned NumStores,
730 EVT MemVT, SDNode *Root, bool AllowVectors);
737 unsigned NumConsecutiveStores, EVT MemVT,
743 unsigned NumConsecutiveStores, EVT MemVT,
1212 EVT MemVT = LD->getMemoryVT();
1218 MemVT, LD->getMemOperand());
1449 EVT MemVT = LD->getMemoryVT();
1454 MemVT, LD->getMemOperand());
5229 ISD::LoadExtType ExtType, EVT &MemVT,
    [all...]
SelectionDAG.cpp 7034 SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
7038 ID.AddInteger(MemVT.getRawBits());
7048 VTList, MemVT, MMO);
7057 EVT MemVT, SDVTList VTs, SDValue Chain,
7065 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
7068 SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
7093 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
7096 SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
7103 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
7120 EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment
    [all...]
LegalizeDAG.cpp 510 EVT MemVT = ST->getMemoryVT();
512 if (!TLI.allowsMemoryAccessForAlignment(*DAG.getContext(), DL, MemVT,
620 EVT MemVT = ST->getMemoryVT();
623 if (!TLI.allowsMemoryAccessForAlignment(*DAG.getContext(), DL, MemVT,
681 EVT MemVT = LD->getMemoryVT();
685 if (!TLI.allowsMemoryAccessForAlignment(*DAG.getContext(), DL, MemVT,
866 EVT MemVT = LD->getMemoryVT();
868 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT,
1436 EVT MemVT = isa<BuildVectorSDNode>(Node) ? VT.getVectorElementType()
1446 unsigned TypeByteSize = MemVT.getSizeInBits() / 8
    [all...]
SelectionDAGBuilder.cpp 2453 EVT MemVT = TLI.getMemValueType(DAG.getDataLayout(), CB.CmpLHS->getType());
2472 if (CondLHS.getValueType() != MemVT) {
2473 CondLHS = DAG.getPtrExtOrTrunc(CondLHS, getCurSDLoc(), MemVT);
2474 CondRHS = DAG.getPtrExtOrTrunc(CondRHS, getCurSDLoc(), MemVT);
3196 EVT MemVT =
3202 if (Op1.getValueType() != MemVT) {
3203 Op1 = DAG.getPtrExtOrTrunc(Op1, getCurSDLoc(), MemVT);
3204 Op2 = DAG.getPtrExtOrTrunc(Op2, getCurSDLoc(), MemVT);
4579 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
4580 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other)
    [all...]
LegalizeVectorTypes.cpp 1090 void DAGTypeLegalizer::IncrementPointer(MemSDNode *N, EVT MemVT,
1094 unsigned IncrementSize = MemVT.getSizeInBits().getKnownMinSize() / 8;
1096 if (MemVT.isScalableVector()) {
5161 EVT MemVT((MVT::SimpleValueType) VT);
5162 unsigned MemVTWidth = MemVT.getSizeInBits();
5163 if (MemVT.getSizeInBits() <= WidenEltWidth)
5165 auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
5173 return MemVT;
5174 RetVT = MemVT;
5184 EVT MemVT = (MVT::SimpleValueType) VT
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 1238 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT;
1239 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
1248 CurDAG->getEntryNode(), dl, N->getOperand(0), MemTmp, MPI, MemVT);
1250 MemTmp, MPI, MemVT);
1294 MVT MemVT = (N->getOpcode() == ISD::STRICT_FP_ROUND) ? DstVT : SrcVT;
1295 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
1308 Store = CurDAG->getMemIntrinsicNode(X86ISD::FST, dl, VTs, Ops, MemVT,
1317 assert(SrcVT == MemVT && "Unexpected VT!");
1326 X86ISD::FLD, dl, VTs, Ops, MemVT, MPI,
1334 assert(DstVT == MemVT && "Unexpected VT!")
    [all...]
X86ISelLowering.h 987 bool mergeStoresAfterLegalization(EVT MemVT) const override {
988 return !MemVT.isVector();
991 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
1322 bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem,
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelDAGToDAG.cpp 1345 EVT MemVT = StoreNode->getMemoryVT();
1355 if (MemVT == MVT::i32)
1357 else if (MemVT == MVT::i64)
1366 if (MemVT == MVT::i32)
1368 else if (MemVT == MVT::i64)
1390 Operand = CurDAG->getTargetConstant(OperandV, DL, MemVT);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.h 702 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
711 return (MemVT.getSizeInBits() <= 64);
AArch64ISelLowering.cpp 4181 void selectGatherScatterAddrMode(SDValue &BasePtr, SDValue &Index, EVT MemVT,
4209 unsigned ScalarSizeInBytes = MemVT.getScalarSizeInBits() / 8;
4249 EVT MemVT = MGT->getMemoryVT();
4250 SDValue InputVT = DAG.getValueType(MemVT);
4260 InputVT = DAG.getValueType(MemVT.changeVectorElementTypeToInteger());
4269 selectGatherScatterAddrMode(BasePtr, Index, MemVT, Opcode,
4309 EVT MemVT = MSC->getMemoryVT();
4310 SDValue InputVT = DAG.getValueType(MemVT);
4320 InputVT = DAG.getValueType(MemVT.changeVectorElementTypeToInteger());
4327 selectGatherScatterAddrMode(BasePtr, Index, MemVT, Opcode
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.h 667 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
670 return (MemVT.getSizeInBits() <= 32);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 2650 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2660 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2667 EVT MemVT = LD->getMemoryVT();
2672 // Return if load is aligned or if MemVT is neither i32 nor i64.
2673 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2674 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2732 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2741 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2793 EVT MemVT = SD->getMemoryVT()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 707 Info.memVT = MVT::i32;
721 Info.memVT = MVT::i32;
729 Info.memVT = MVT::i64;
738 Info.memVT = Intrinsic == Intrinsic::wasm_load32_zero ? MVT::i32 : MVT::i64;
752 MVT MemVT;
756 MemVT = MVT::i8;
760 MemVT = MVT::i16;
764 MemVT = MVT::i32;
768 MemVT = MVT::i64;
784 Info.memVT = MemVT
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 2885 EVT MemVT = LD->getMemoryVT();
2886 if (!MemVT.isSimple())
2888 switch(MemVT.getSimpleVT().SimpleTy) {
8156 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
8180 if (LD->getMemoryVT() != MemVT)
10441 EVT MemVT = AtomicNode->getMemoryVT();
10442 if (MemVT.getSizeInBits() >= 32)
10447 auto HighBits = APInt::getHighBitsSet(32, 32 - MemVT.getSizeInBits());
10452 unsigned MaskVal = (1 << MemVT.getSizeInBits()) - 1;
10465 (MemVT == MVT::i8) ? PPCISD::ATOMIC_CMP_SWAP_8 : PPCISD::ATOMIC_CMP_SWAP_16
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelDAGToDAG.cpp 1147 EVT MemVT = Ld->getMemoryVT();
1149 if (MemVT.getStoreSize() != VT.getVectorElementType().getStoreSize())

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