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    Searched refs:MidVT (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeDAG.cpp 4366 MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt);
4367 assert(TLI.isTypeLegal(MidVT) && "unexpected");
4368 return MidVT;
4779 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4784 NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op));
4812 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4813 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4833 SDValue NewVec = DAG.getBuildVector(MidVT, SL, NewOps);
4858 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4859 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements()
    [all...]
LegalizeFloatTypes.cpp 527 EVT MidVT = TLI.getTypeToTransformTo(*DAG.getContext(), MVT::f32);
532 SDValue Res32 = TLI.makeLibCall(DAG, RTLIB::FPEXT_F16_F32, MidVT, Op,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelLowering.cpp 3260 EVT MidVT = VT.isVector() ?
3264 EVT NewShiftVT = getShiftAmountTy(MidVT, DAG.getDataLayout());
3265 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT,
3274 SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 13066 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16);
13067 SmallVector<int, 8> Mask(MidVT.getVectorNumElements());
13072 MidVT, dl,
13073 DAG.getNode(ISD::BITCAST, dl, MidVT, N00),
13074 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask));
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp     [all...]

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