HomeSort by: relevance | last modified time | path
    Searched refs:Mov (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/compiler_rt/dist/lib/asan/tests/
asan_asm_test.cc 39 #define DECLARE_ASM_WRITE(Type, Size, Mov, Reg) \
42 Mov " %[val], (%[ptr]) \n\t" \
49 #define DECLARE_ASM_READ(Type, Size, Mov, Reg) \
53 Mov " (%[ptr]), %[res] \n\t" \
82 #define DECLARE_ASM_WRITE(Type, Size, Mov, Reg) \
85 Mov " %[val], (%[ptr]) \n\t" \
92 #define DECLARE_ASM_READ(Type, Size, Mov, Reg) \
96 Mov " (%[ptr]), %[res] \n\t" \
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ExpandSpecialInstrs.cpp 89 MachineInstr *Mov = TII->buildMovInstr(&MBB, I,
94 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(),
97 Mov->getOperand(MovPredSelIdx).setReg(
SIPreEmitPeephole.cpp 85 const unsigned Mov = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
154 // Replace AND with MOV
156 BuildMI(*A->getParent(), *A, A->getDebugLoc(), TII->get(Mov), CondReg)
159 BuildMI(*A->getParent(), *A, A->getDebugLoc(), TII->get(Mov), CondReg)
R600InstrInfo.cpp 58 buildDefaultInstruction(MBB, MI, R600::MOV,
65 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, R600::MOV,
88 case R600::MOV:
1115 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, R600::MOV,
1119 setImmOperand(*Mov, R600::OpName::dst_rel, 1);
1120 return Mov;
1147 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, R600::MOV,
1152 setImmOperand(*Mov, R600::OpName::src0_rel, 1)
    [all...]
SILoadStoreOptimizer.cpp 1665 MachineInstr *Mov =
1669 (void)Mov;
1670 LLVM_DEBUG(dbgs() << " "; Mov->dump());
AMDGPUISelDAGToDAG.cpp 1004 SDNode *Mov = CurDAG->getMachineNode(
1007 return SDValue(Mov, 0);
AMDGPUInstructionSelector.cpp 1160 unsigned Mov = DstRB->getID() == AMDGPU::SGPRRegBankID ?
1166 auto MIB = BuildMI(*MBB, &I, DL, TII.get(Mov), DstReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp 1017 MachineInstrBuilder Mov;
1035 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
1038 Mov.addReg(Src);
1042 addUnpredicatedMveVpredROp(Mov, Dst);
1044 Mov = Mov.add(predOps(ARMCC::AL));
1047 Mov = Mov.add(condCodeOp());
1050 Mov->addRegisterDefined(DestReg, TRI);
1052 Mov->addRegisterKilled(SrcReg, TRI)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 155 /// vector register \p Dst. (E.g. a MOV, or a load from a constant pool.)
2070 // MOV or load from a constant pool.
2405 // Either emit a FMOV, or emit a copy to emit a normal mov.
2428 // Nope. Emit a copy and use a normal mov instead.
2976 // For the 32-bit -> 64-bit case, we can emit a mov (ORRWrs)
4764 auto Mov =
4766 constrainSelectedInstRegOperands(*Mov, TII, TRI, RBI);
4767 return &*Mov;
4771 auto Mov =
4776 .addReg(Mov.getReg(0), 0, AArch64::dsub)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 7645 // The cost is actually exactly the same for mov+fmov vs. adrp+ldr;
7646 // however the mov+fmov sequence is always better because of the reduced
7779 // M - Constant that can be used as a 32-bit MOV immediate
7780 // N - Constant that can be used as a 64-bit MOV immediate
8073 // been removed and MOV should be used). So these constraints have to
8087 // with the MOV (immediate) alias. As well as the logical immediates they
9304 SDValue Mov = DAG.getNode(NewOp, dl, MovTy,
9306 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
9343 SDValue Mov;
9346 Mov = DAG.getNode(NewOp, dl, MovTy, *LHS
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 8039 SDValue Mov = DAG.getNode(PPCISD::MFVSR, dl, Op.getValueType(), Conv);
8041 return DAG.getMergeValues({Mov, Conv.getValue(1)}, dl);
8043 return Mov;
8305 SDValue Mov = DAG.getNode(MovOpc, dl, MVT::f64, Src);
8306 return convertIntToFP(Op, Mov, DAG, Subtarget);

Completed in 81 milliseconds