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    Searched refs:MovOpc (Results 1 - 11 of 11) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsAsmPrinter.cpp 906 unsigned MovOpc, unsigned Reg1,
914 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1);
915 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2);
923 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
926 EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
929 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
932 EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
933 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
936 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
939 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE)
    [all...]
MipsSEInstrInfo.h 115 unsigned CvtOpc, unsigned MovOpc, bool IsI64) const;
MipsAsmPrinter.h 99 void EmitMovFPIntPair(const MCSubtargetInfo &STI, unsigned MovOpc,
MipsSEInstrInfo.cpp 759 unsigned CvtOpc, unsigned MovOpc,
761 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SILateBranchLowering.cpp 38 unsigned MovOpc;
124 MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
168 BuildMI(*EarlyExitBlock, EarlyExitBlock->end(), DL, TII->get(MovOpc),
SIRegisterInfo.cpp 107 unsigned MovOpc;
124 MovOpc = AMDGPU::S_MOV_B32;
128 MovOpc = AMDGPU::S_MOV_B64;
192 BuildMI(MBB, MI, DL, TII.get(MovOpc), SavedExecReg).addReg(ExecReg);
193 auto I = BuildMI(MBB, MI, DL, TII.get(MovOpc), ExecReg).addImm(VGPRLanes);
227 auto I = BuildMI(MBB, MI, DL, TII.get(MovOpc), ExecReg)
681 unsigned MovOpc = ST.enableFlatScratch() ? AMDGPU::S_MOV_B32
689 BuildMI(*MBB, Ins, DL, TII->get(MovOpc), BaseReg)
702 BuildMI(*MBB, Ins, DL, TII->get(MovOpc), FIReg)
SIWholeQuadMode.cpp 976 unsigned MovOpc = ST->isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
977 NewTerm = BuildMI(MBB, &MI, DL, TII->get(MovOpc), Exec).addImm(0);
AMDGPUInstructionSelector.cpp 145 unsigned MovOpc =
147 BuildMI(*BB, &I, DL, TII.get(MovOpc), DstReg)
1907 unsigned MovOpc = IsVALU ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32;
1911 BuildMI(*MBB, I, DL, TII.get(MovOpc), ImmReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86IndirectThunks.cpp 244 const unsigned MovOpc = Is64Bit ? X86::MOV64mr : X86::MOV32mr;
246 addRegOffset(BuildMI(CallTarget, DebugLoc(), TII->get(MovOpc)), SPReg, false,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 2401 const unsigned MovOpc =
2452 I.setDesc(TII.get(MovOpc));
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 8304 unsigned MovOpc = (WordInt && !Signed) ? PPCISD::MTVSRZ : PPCISD::MTVSRA;
8305 SDValue Mov = DAG.getNode(MovOpc, dl, MVT::f64, Src);

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