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    Searched refs:MulOpc (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
MLxExpansionPass.cpp 68 unsigned MulOpc, unsigned AddSubOpc,
270 unsigned MulOpc, unsigned AddSubOpc,
284 const MCInstrDesc &MCID1 = TII->get(MulOpc);
354 unsigned MulOpc, AddSubOpc;
357 MulOpc, AddSubOpc, NegAcc, HasLane) ||
361 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane);
ARMBaseInstrInfo.h 505 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
ARMBaseInstrInfo.cpp 84 uint16_t MulOpc; // Expanded multiplication opcode
91 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
120 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
4889 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
4897 MulOpc = Entry.MulOpc;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp 4533 unsigned MulOpc, unsigned ZeroReg) {
4534 return canCombine(MBB, MO, MulOpc, ZeroReg, true);
4540 unsigned MulOpc) {
4541 return canCombine(MBB, MO, MulOpc);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelLowering.cpp 3291 unsigned MulOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
3292 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp     [all...]

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