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    Searched refs:N0Opc (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 1424 unsigned N0Opc = And.getMachineOpcode();
1425 if (N0Opc == X86::AND8rr || N0Opc == X86::AND16rr ||
1426 N0Opc == X86::AND32rr || N0Opc == X86::AND64rr) {
1435 if (N0Opc == X86::AND8rm || N0Opc == X86::AND16rm ||
1436 N0Opc == X86::AND32rm || N0Opc == X86::AND64rm) {
1438 switch (N0Opc) {
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 13044 unsigned N0Opc = N0->getOpcode(), N1Opc = N1->getOpcode();
13057 if (N->getNumOperands() == 2 && N0Opc == ISD::TRUNCATE &&
13094 if (N->getNumOperands() == 2 && N0Opc == N1Opc &&
13095 (N0Opc == AArch64ISD::URHADD || N0Opc == AArch64ISD::SRHADD ||
13096 N0Opc == AArch64ISD::UHADD || N0Opc == AArch64ISD::SHADD)) {
13125 return DAG.getNode(N0Opc, dl, VT, N00Source, N01Source);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
TargetLowering.cpp 3618 unsigned N0Opc = N0->getOpcode();
3619 bool SExt = (N0Opc == ISD::SIGN_EXTEND);
3622 (N0Opc == ISD::ZERO_EXTEND || N0Opc == ISD::SIGN_EXTEND) &&

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