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  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/
meson-gxl-s805x-libretech-ac.dts 249 "SPI NOR MOSI", "SPI NOR MISO", "SPI NOR Clk",
250 "", "SPI NOR Chip Select",
304 compatible = "jedec,spi-nor";
meson-gxm-khadas-vim2.dts 369 * EMMC_DS pin is shared between SPI NOR CS and eMMC Data Strobe
380 compatible = "winbond,w25q16", "jedec,spi-nor";
meson-khadas-vim3.dtsi 451 * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR CS
464 compatible = "winbond,w25q128fw", "jedec,spi-nor";
meson-g12b-odroid-n2.dtsi 599 * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins
613 compatible = "mxicy,mx25u6435f", "jedec,spi-nor";
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
mt7629-rfb.dts 109 compatible = "jedec,spi-nor";
196 /* SPI-NOR is shared pin with serial NAND */
204 /* Serial NAND is shared pin with SPI-NOR */
imx6qdl-dfi-fs700-m60.dtsi 41 compatible = "sst,sst25vf040b", "jedec,spi-nor";
152 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
armada-xp-openblocks-ax3-4.dts 56 /* NOR 128 MiB */
57 nor@0 {
armada-xp-db.dts 67 /* NOR 16 MiB */
68 nor@0 {
241 compatible = "m25p64", "jedec,spi-nor";
armada-xp-gp.dts 85 /* NOR 16 MiB */
86 nor@0 {
226 compatible = "n25q128a13", "jedec,spi-nor";
logicpd-som-lv-baseboard.dtsi 66 2 0 0x10000000 0x2000000>; /* CS2: 32MB for NOR */
vf610-zii-cfu1.dts 99 * Some CFU1s come with SPI-NOR chip DNPed, so we leave this
108 compatible = "m25p128", "jedec,spi-nor";
vf610-zii-ssmb-spu3.dts 74 * Some SPU3s come with SPI-NOR chip DNPed, so we leave this
83 compatible = "m25p128", "jedec,spi-nor";
am335x-nano.dts 248 ranges = <0 0 0x08000000 0x08000000>, /* CS0: NOR 128M */
251 nor@0,0 {
305 +------------+-->0x08000000-> NOR end (Free end)
zynq-7000.dtsi 262 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
263 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
imx6qdl-sabreauto.dtsi 273 status = "disabled"; /* pin conflict with WEIM NOR */
278 compatible = "st,m25p32", "jedec,spi-nor";
852 status = "disabled"; /* pin conflict with SPI NOR */
854 nor@0,0 {
versatile-ab.dts 160 /* 64 MiB NOR flash in non-interleaved chips */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
fsl-ls1043a-qds.dts 45 /* NOR, NAND Flashes and FPGA on board */
51 nor@0,0 {
fsl-ls1046a-qds.dts 42 compatible = "n25q128a11", "jedec,spi-nor";
50 compatible = "sst25wf040b", "jedec,spi-nor";
60 compatible = "en25s64", "jedec,spi-nor";
136 /* NOR, NAND Flashes and FPGA on board */
142 nor@0,0 {
fsl-ls1043a-rdb.dts 59 /* NOR, NAND Flashes and FPGA on board */
64 nor@0,0 {
94 compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */
fsl-ls1088a-ten64.dts 290 compatible = "jedec,spi-nor";
355 * (this would use the same layout as the 8MiB NOR flash)
  /src/sys/external/bsd/sljit/dist/sljit_src/
sljitNativeMIPS_32.c 127 FAIL_IF(push_inst(compiler, NOR | S(src2) | T(src2) | DA(EQUAL_FLAG), EQUAL_FLAG));
129 FAIL_IF(push_inst(compiler, NOR | S(src2) | T(src2) | D(dst), DR(dst)));
168 FAIL_IF(push_inst(compiler, NOR | S(src1) | T(src1) | DA(EQUAL_FLAG), EQUAL_FLAG));
310 FAIL_IF(push_inst(compiler, NOR | S(src1) | T(src1) | DA(EQUAL_FLAG), EQUAL_FLAG));
sljitNativeMIPS_64.c 218 FAIL_IF(push_inst(compiler, NOR | S(src2) | T(src2) | DA(EQUAL_FLAG), EQUAL_FLAG));
220 FAIL_IF(push_inst(compiler, NOR | S(src2) | T(src2) | D(dst), DR(dst)));
259 FAIL_IF(push_inst(compiler, NOR | S(src1) | T(src1) | DA(EQUAL_FLAG), EQUAL_FLAG));
401 FAIL_IF(push_inst(compiler, NOR | S(src1) | T(src1) | DA(EQUAL_FLAG), EQUAL_FLAG));
sljitNativePPC_32.c 89 return push_inst(compiler, NOR | RC(flags) | S(src2) | A(dst) | B(src2));
sljitNativePPC_64.c 205 return push_inst(compiler, NOR | RC(flags) | S(src2) | A(dst) | B(src2));
  /src/sys/arch/mips/mips/
bds_emul.S 18 * 3. Neither the name of the University nor the names of its contributors
317 PTR_WORD bcemul_special_gen3op # 047 NOR
410 jr ra; nor t0, v0, v1 # 047 NOR

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