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Searched refs:NV_VIO_SR_CLOCK_INDEX (Results 1 - 5 of 5) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/
hw.h	`247 uint8_t seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); 251 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 \| 0x20); 254 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); /* reenable display */`
nouveau_dispnv04_dac.c	`161 saved_seq1 = NVReadVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX); 162 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1 & ~0x20); 228 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1);`
nouveau_dispnv04_hw.c	`121 seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); 125 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 \| 0x20); 127 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);`
nouveau_dispnv04_crtc.c	`226 seq1 \|= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); 227 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); 335 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; 337 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;`
nvreg.h	`135 # define NV_VIO_SR_CLOCK_INDEX 0x01`

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