1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/Support/Compiler.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/MathExtras.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &CStream) const override; 141 142 private: 143 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 144 ArrayRef<uint8_t> Bytes, uint64_t Address, 145 raw_ostream &CStream) const; 146 147 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 148 ArrayRef<uint8_t> Bytes, uint64_t Address, 149 raw_ostream &CStream) const; 150 151 mutable ITStatus ITBlock; 152 mutable VPTStatus VPTBlock; 153 154 DecodeStatus AddThumbPredicate(MCInst&) const; 155 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 156 }; 157 158 } // end anonymous namespace 159 160 static bool Check(DecodeStatus &Out, DecodeStatus In) { 161 switch (In) { 162 case MCDisassembler::Success: 163 // Out stays the same. 164 return true; 165 case MCDisassembler::SoftFail: 166 Out = In; 167 return true; 168 case MCDisassembler::Fail: 169 Out = In; 170 return false; 171 } 172 llvm_unreachable("Invalid DecodeStatus!"); 173 } 174 175 // Forward declare these because the autogenerated code will reference them. 176 // Definitions are further down. 177 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus 186 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 189 unsigned RegNo, uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 192 unsigned RegNo, uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 195 unsigned RegNo, uint64_t Address, 196 const void *Decoder); 197 static DecodeStatus DecodeGPRwithZRnospRegisterClass( 198 MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 210 uint64_t Address, 211 const void *Decoder); 212 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 223 unsigned RegNo, 224 uint64_t Address, 225 const void *Decoder); 226 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 237 unsigned RegNo, uint64_t Address, 238 const void *Decoder); 239 240 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 251 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 256 unsigned Insn, 257 uint64_t Address, 258 const void *Decoder); 259 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 260 uint64_t Address, const void *Decoder); 261 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 266 uint64_t Address, const void *Decoder); 267 268 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 269 unsigned Insn, 270 uint64_t Adddress, 271 const void *Decoder); 272 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 343 uint64_t Address, const void *Decoder); 344 template<int shift> 345 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 346 uint64_t Address, const void *Decoder); 347 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 380 uint64_t Address, const void *Decoder); 381 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 384 uint64_t Address, const void *Decoder); 385 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 386 uint64_t Address, const void *Decoder); 387 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 388 uint64_t Address, const void *Decoder); 389 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 390 uint64_t Address, const void *Decoder); 391 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 392 uint64_t Address, const void *Decoder); 393 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 394 uint64_t Address, const void *Decoder); 395 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 396 uint64_t Address, const void *Decoder); 397 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 398 unsigned Val, 399 uint64_t Address, 400 const void *Decoder); 401 402 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 403 uint64_t Address, const void *Decoder); 404 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 405 uint64_t Address, const void *Decoder); 406 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 407 uint64_t Address, const void *Decoder); 408 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 409 uint64_t Address, const void *Decoder); 410 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 411 uint64_t Address, const void *Decoder); 412 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 413 uint64_t Address, const void *Decoder); 414 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 415 uint64_t Address, const void *Decoder); 416 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 417 uint64_t Address, const void *Decoder); 418 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 419 uint64_t Address, const void *Decoder); 420 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 421 uint64_t Address, const void *Decoder); 422 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 423 uint64_t Address, const void* Decoder); 424 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 425 uint64_t Address, const void* Decoder); 426 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 427 uint64_t Address, const void* Decoder); 428 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 429 uint64_t Address, const void* Decoder); 430 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 431 uint64_t Address, const void *Decoder); 432 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 433 uint64_t Address, const void *Decoder); 434 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 435 uint64_t Address, const void *Decoder); 436 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 437 uint64_t Address, 438 const void *Decoder); 439 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 440 uint64_t Address, const void *Decoder); 441 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 442 uint64_t Address, const void *Decoder); 443 template<int shift> 444 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 445 uint64_t Address, const void *Decoder); 446 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 447 uint64_t Address, const void *Decoder); 448 template<int shift> 449 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 450 uint64_t Address, const void *Decoder); 451 template<int shift, int WriteBack> 452 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 453 uint64_t Address, const void *Decoder); 454 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 455 uint64_t Address, const void *Decoder); 456 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 457 uint64_t Address, const void *Decoder); 458 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 459 uint64_t Address, const void *Decoder); 460 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 461 uint64_t Address, const void *Decoder); 462 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 463 uint64_t Address, const void *Decoder); 464 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 465 uint64_t Address, const void *Decoder); 466 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 467 uint64_t Address, const void *Decoder); 468 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 469 uint64_t Address, const void *Decoder); 470 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 471 uint64_t Address, const void *Decoder); 472 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 473 uint64_t Address, const void *Decoder); 474 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 475 uint64_t Address, const void *Decoder); 476 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 477 uint64_t Address, const void *Decoder); 478 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 479 uint64_t Address, const void *Decoder); 480 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 481 uint64_t Address, const void *Decoder); 482 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 483 uint64_t Address, const void *Decoder); 484 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 485 uint64_t Address, const void *Decoder); 486 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 487 uint64_t Address, const void *Decoder); 488 489 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 490 uint64_t Address, const void *Decoder); 491 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 492 uint64_t Address, const void *Decoder); 493 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 494 uint64_t Address, const void *Decoder); 495 496 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 497 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 498 uint64_t Address, const void *Decoder); 499 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 500 uint64_t Address, 501 const void *Decoder); 502 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 503 uint64_t Address, 504 const void *Decoder); 505 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 506 const void *Decoder); 507 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 508 uint64_t Address, 509 const void *Decoder); 510 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 511 const void *Decoder); 512 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 513 uint64_t Address, const void *Decoder); 514 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 515 uint64_t Address, const void *Decoder); 516 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 517 uint64_t Address, 518 const void *Decoder); 519 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 520 uint64_t Address, 521 const void *Decoder); 522 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 523 uint64_t Address, 524 const void *Decoder); 525 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 526 unsigned Val, 527 uint64_t Address, 528 const void *Decoder); 529 template<bool Writeback> 530 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 531 uint64_t Address, 532 const void *Decoder); 533 template<int shift> 534 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 535 uint64_t Address, const void *Decoder); 536 template<int shift> 537 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 538 uint64_t Address, const void *Decoder); 539 template<int shift> 540 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 541 uint64_t Address, const void *Decoder); 542 template<unsigned MinLog, unsigned MaxLog> 543 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 544 uint64_t Address, 545 const void *Decoder); 546 template<unsigned start> 547 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 548 uint64_t Address, 549 const void *Decoder); 550 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 551 uint64_t Address, 552 const void *Decoder); 553 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 554 uint64_t Address, 555 const void *Decoder); 556 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 557 uint64_t Address, const void *Decoder); 558 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 559 uint64_t Address, const void *Decoder); 560 template<bool scalar, OperandDecoder predicate_decoder> 561 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, 562 uint64_t Address, const void *Decoder); 563 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, 564 uint64_t Address, const void *Decoder); 565 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 566 uint64_t Address, const void *Decoder); 567 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 568 uint64_t Address, 569 const void *Decoder); 570 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 571 uint64_t Address, const void *Decoder); 572 573 #include "ARMGenDisassemblerTables.inc" 574 575 static MCDisassembler *createARMDisassembler(const Target &T, 576 const MCSubtargetInfo &STI, 577 MCContext &Ctx) { 578 return new ARMDisassembler(STI, Ctx); 579 } 580 581 // Post-decoding checks 582 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 583 uint64_t Address, raw_ostream &CS, 584 uint32_t Insn, 585 DecodeStatus Result) { 586 switch (MI.getOpcode()) { 587 case ARM::HVC: { 588 // HVC is undefined if condition = 0xf otherwise upredictable 589 // if condition != 0xe 590 uint32_t Cond = (Insn >> 28) & 0xF; 591 if (Cond == 0xF) 592 return MCDisassembler::Fail; 593 if (Cond != 0xE) 594 return MCDisassembler::SoftFail; 595 return Result; 596 } 597 case ARM::t2ADDri: 598 case ARM::t2ADDri12: 599 case ARM::t2ADDrr: 600 case ARM::t2ADDrs: 601 case ARM::t2SUBri: 602 case ARM::t2SUBri12: 603 case ARM::t2SUBrr: 604 case ARM::t2SUBrs: 605 if (MI.getOperand(0).getReg() == ARM::SP && 606 MI.getOperand(1).getReg() != ARM::SP) 607 return MCDisassembler::SoftFail; 608 return Result; 609 default: return Result; 610 } 611 } 612 613 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 614 ArrayRef<uint8_t> Bytes, 615 uint64_t Address, 616 raw_ostream &CS) const { 617 if (STI.getFeatureBits()[ARM::ModeThumb]) 618 return getThumbInstruction(MI, Size, Bytes, Address, CS); 619 return getARMInstruction(MI, Size, Bytes, Address, CS); 620 } 621 622 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 623 ArrayRef<uint8_t> Bytes, 624 uint64_t Address, 625 raw_ostream &CS) const { 626 CommentStream = &CS; 627 628 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 629 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 630 "mode!"); 631 632 // We want to read exactly 4 bytes of data. 633 if (Bytes.size() < 4) { 634 Size = 0; 635 return MCDisassembler::Fail; 636 } 637 638 // Encoded as a small-endian 32-bit word in the stream. 639 uint32_t Insn = 640 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 641 642 // Calling the auto-generated decoder function. 643 DecodeStatus Result = 644 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 645 if (Result != MCDisassembler::Fail) { 646 Size = 4; 647 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 648 } 649 650 struct DecodeTable { 651 const uint8_t *P; 652 bool DecodePred; 653 }; 654 655 const DecodeTable Tables[] = { 656 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 657 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 658 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 659 {DecoderTablev8Crypto32, false}, 660 }; 661 662 for (auto Table : Tables) { 663 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 664 if (Result != MCDisassembler::Fail) { 665 Size = 4; 666 // Add a fake predicate operand, because we share these instruction 667 // definitions with Thumb2 where these instructions are predicable. 668 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 669 return MCDisassembler::Fail; 670 return Result; 671 } 672 } 673 674 Result = 675 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 676 if (Result != MCDisassembler::Fail) { 677 Size = 4; 678 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 679 } 680 681 Size = 4; 682 return MCDisassembler::Fail; 683 } 684 685 namespace llvm { 686 687 extern const MCInstrDesc ARMInsts[]; 688 689 } // end namespace llvm 690 691 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 692 /// immediate Value in the MCInst. The immediate Value has had any PC 693 /// adjustment made by the caller. If the instruction is a branch instruction 694 /// then isBranch is true, else false. If the getOpInfo() function was set as 695 /// part of the setupForSymbolicDisassembly() call then that function is called 696 /// to get any symbolic information at the Address for this instruction. If 697 /// that returns non-zero then the symbolic information it returns is used to 698 /// create an MCExpr and that is added as an operand to the MCInst. If 699 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 700 /// Value is done and if a symbol is found an MCExpr is created with that, else 701 /// an MCExpr with Value is created. This function returns true if it adds an 702 /// operand to the MCInst and false otherwise. 703 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 704 bool isBranch, uint64_t InstSize, 705 MCInst &MI, const void *Decoder) { 706 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 707 // FIXME: Does it make sense for value to be negative? 708 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 709 /* Offset */ 0, InstSize); 710 } 711 712 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 713 /// referenced by a load instruction with the base register that is the Pc. 714 /// These can often be values in a literal pool near the Address of the 715 /// instruction. The Address of the instruction and its immediate Value are 716 /// used as a possible literal pool entry. The SymbolLookUp call back will 717 /// return the name of a symbol referenced by the literal pool's entry if 718 /// the referenced address is that of a symbol. Or it will return a pointer to 719 /// a literal 'C' string if the referenced address of the literal pool's entry 720 /// is an address into a section with 'C' string literals. 721 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 722 const void *Decoder) { 723 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 724 Dis->tryAddingPcLoadReferenceComment(Value, Address); 725 } 726 727 // Thumb1 instructions don't have explicit S bits. Rather, they 728 // implicitly set CPSR. Since it's not represented in the encoding, the 729 // auto-generated decoder won't inject the CPSR operand. We need to fix 730 // that as a post-pass. 731 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 732 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 733 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 734 MCInst::iterator I = MI.begin(); 735 for (unsigned i = 0; i < NumOps; ++i, ++I) { 736 if (I == MI.end()) break; 737 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 738 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 739 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 740 return; 741 } 742 } 743 744 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 745 } 746 747 static bool isVectorPredicable(unsigned Opcode) { 748 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 749 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 750 for (unsigned i = 0; i < NumOps; ++i) { 751 if (ARM::isVpred(OpInfo[i].OperandType)) 752 return true; 753 } 754 return false; 755 } 756 757 // Most Thumb instructions don't have explicit predicates in the 758 // encoding, but rather get their predicates from IT context. We need 759 // to fix up the predicate operands using this context information as a 760 // post-pass. 761 MCDisassembler::DecodeStatus 762 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 763 MCDisassembler::DecodeStatus S = Success; 764 765 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 766 767 // A few instructions actually have predicates encoded in them. Don't 768 // try to overwrite it if we're seeing one of those. 769 switch (MI.getOpcode()) { 770 case ARM::tBcc: 771 case ARM::t2Bcc: 772 case ARM::tCBZ: 773 case ARM::tCBNZ: 774 case ARM::tCPS: 775 case ARM::t2CPS3p: 776 case ARM::t2CPS2p: 777 case ARM::t2CPS1p: 778 case ARM::t2CSEL: 779 case ARM::t2CSINC: 780 case ARM::t2CSINV: 781 case ARM::t2CSNEG: 782 case ARM::tMOVSr: 783 case ARM::tSETEND: 784 // Some instructions (mostly conditional branches) are not 785 // allowed in IT blocks. 786 if (ITBlock.instrInITBlock()) 787 S = SoftFail; 788 else 789 return Success; 790 break; 791 case ARM::t2HINT: 792 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 793 S = SoftFail; 794 break; 795 case ARM::tB: 796 case ARM::t2B: 797 case ARM::t2TBB: 798 case ARM::t2TBH: 799 // Some instructions (mostly unconditional branches) can 800 // only appears at the end of, or outside of, an IT. 801 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 802 S = SoftFail; 803 break; 804 default: 805 break; 806 } 807 808 // Warn on non-VPT predicable instruction in a VPT block and a VPT 809 // predicable instruction in an IT block 810 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 811 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 812 S = SoftFail; 813 814 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 815 // assume a predicate of AL. 816 unsigned CC = ARMCC::AL; 817 unsigned VCC = ARMVCC::None; 818 if (ITBlock.instrInITBlock()) { 819 CC = ITBlock.getITCC(); 820 ITBlock.advanceITState(); 821 } else if (VPTBlock.instrInVPTBlock()) { 822 VCC = VPTBlock.getVPTPred(); 823 VPTBlock.advanceVPTState(); 824 } 825 826 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 827 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 828 829 MCInst::iterator CCI = MI.begin(); 830 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 831 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 832 } 833 834 if (ARMInsts[MI.getOpcode()].isPredicable()) { 835 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 836 ++CCI; 837 if (CC == ARMCC::AL) 838 MI.insert(CCI, MCOperand::createReg(0)); 839 else 840 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 841 } else if (CC != ARMCC::AL) { 842 Check(S, SoftFail); 843 } 844 845 MCInst::iterator VCCI = MI.begin(); 846 unsigned VCCPos; 847 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 848 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 849 } 850 851 if (isVectorPredicable(MI.getOpcode())) { 852 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 853 ++VCCI; 854 if (VCC == ARMVCC::None) 855 MI.insert(VCCI, MCOperand::createReg(0)); 856 else 857 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 858 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 859 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 860 VCCPos + 2, MCOI::TIED_TO); 861 assert(TiedOp >= 0 && 862 "Inactive register in vpred_r is not tied to an output!"); 863 // Copy the operand to ensure it's not invalidated when MI grows. 864 MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp))); 865 } 866 } else if (VCC != ARMVCC::None) { 867 Check(S, SoftFail); 868 } 869 870 return S; 871 } 872 873 // Thumb VFP instructions are a special case. Because we share their 874 // encodings between ARM and Thumb modes, and they are predicable in ARM 875 // mode, the auto-generated decoder will give them an (incorrect) 876 // predicate operand. We need to rewrite these operands based on the IT 877 // context as a post-pass. 878 void ARMDisassembler::UpdateThumbVFPPredicate( 879 DecodeStatus &S, MCInst &MI) const { 880 unsigned CC; 881 CC = ITBlock.getITCC(); 882 if (CC == 0xF) 883 CC = ARMCC::AL; 884 if (ITBlock.instrInITBlock()) 885 ITBlock.advanceITState(); 886 else if (VPTBlock.instrInVPTBlock()) { 887 CC = VPTBlock.getVPTPred(); 888 VPTBlock.advanceVPTState(); 889 } 890 891 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 892 MCInst::iterator I = MI.begin(); 893 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 894 for (unsigned i = 0; i < NumOps; ++i, ++I) { 895 if (OpInfo[i].isPredicate() ) { 896 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 897 Check(S, SoftFail); 898 I->setImm(CC); 899 ++I; 900 if (CC == ARMCC::AL) 901 I->setReg(0); 902 else 903 I->setReg(ARM::CPSR); 904 return; 905 } 906 } 907 } 908 909 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 910 ArrayRef<uint8_t> Bytes, 911 uint64_t Address, 912 raw_ostream &CS) const { 913 CommentStream = &CS; 914 915 assert(STI.getFeatureBits()[ARM::ModeThumb] && 916 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 917 918 // We want to read exactly 2 bytes of data. 919 if (Bytes.size() < 2) { 920 Size = 0; 921 return MCDisassembler::Fail; 922 } 923 924 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 925 DecodeStatus Result = 926 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 927 if (Result != MCDisassembler::Fail) { 928 Size = 2; 929 Check(Result, AddThumbPredicate(MI)); 930 return Result; 931 } 932 933 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 934 STI); 935 if (Result) { 936 Size = 2; 937 bool InITBlock = ITBlock.instrInITBlock(); 938 Check(Result, AddThumbPredicate(MI)); 939 AddThumb1SBit(MI, InITBlock); 940 return Result; 941 } 942 943 Result = 944 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 945 if (Result != MCDisassembler::Fail) { 946 Size = 2; 947 948 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 949 // the Thumb predicate. 950 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 951 Result = MCDisassembler::SoftFail; 952 953 Check(Result, AddThumbPredicate(MI)); 954 955 // If we find an IT instruction, we need to parse its condition 956 // code and mask operands so that we can apply them correctly 957 // to the subsequent instructions. 958 if (MI.getOpcode() == ARM::t2IT) { 959 unsigned Firstcond = MI.getOperand(0).getImm(); 960 unsigned Mask = MI.getOperand(1).getImm(); 961 ITBlock.setITState(Firstcond, Mask); 962 963 // An IT instruction that would give a 'NV' predicate is unpredictable. 964 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 965 CS << "unpredictable IT predicate sequence"; 966 } 967 968 return Result; 969 } 970 971 // We want to read exactly 4 bytes of data. 972 if (Bytes.size() < 4) { 973 Size = 0; 974 return MCDisassembler::Fail; 975 } 976 977 uint32_t Insn32 = 978 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 979 980 Result = 981 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 982 if (Result != MCDisassembler::Fail) { 983 Size = 4; 984 985 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 986 // the VPT predicate. 987 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 988 Result = MCDisassembler::SoftFail; 989 990 Check(Result, AddThumbPredicate(MI)); 991 992 if (isVPTOpcode(MI.getOpcode())) { 993 unsigned Mask = MI.getOperand(0).getImm(); 994 VPTBlock.setVPTState(Mask); 995 } 996 997 return Result; 998 } 999 1000 Result = 1001 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 1002 if (Result != MCDisassembler::Fail) { 1003 Size = 4; 1004 bool InITBlock = ITBlock.instrInITBlock(); 1005 Check(Result, AddThumbPredicate(MI)); 1006 AddThumb1SBit(MI, InITBlock); 1007 return Result; 1008 } 1009 1010 Result = 1011 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1012 if (Result != MCDisassembler::Fail) { 1013 Size = 4; 1014 Check(Result, AddThumbPredicate(MI)); 1015 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result); 1016 } 1017 1018 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1019 Result = 1020 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1021 if (Result != MCDisassembler::Fail) { 1022 Size = 4; 1023 UpdateThumbVFPPredicate(Result, MI); 1024 return Result; 1025 } 1026 } 1027 1028 Result = 1029 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1030 if (Result != MCDisassembler::Fail) { 1031 Size = 4; 1032 return Result; 1033 } 1034 1035 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1036 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1037 STI); 1038 if (Result != MCDisassembler::Fail) { 1039 Size = 4; 1040 Check(Result, AddThumbPredicate(MI)); 1041 return Result; 1042 } 1043 } 1044 1045 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1046 uint32_t NEONLdStInsn = Insn32; 1047 NEONLdStInsn &= 0xF0FFFFFF; 1048 NEONLdStInsn |= 0x04000000; 1049 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1050 Address, this, STI); 1051 if (Result != MCDisassembler::Fail) { 1052 Size = 4; 1053 Check(Result, AddThumbPredicate(MI)); 1054 return Result; 1055 } 1056 } 1057 1058 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1059 uint32_t NEONDataInsn = Insn32; 1060 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1061 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1062 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1063 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1064 Address, this, STI); 1065 if (Result != MCDisassembler::Fail) { 1066 Size = 4; 1067 Check(Result, AddThumbPredicate(MI)); 1068 return Result; 1069 } 1070 1071 uint32_t NEONCryptoInsn = Insn32; 1072 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1073 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1074 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1075 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1076 Address, this, STI); 1077 if (Result != MCDisassembler::Fail) { 1078 Size = 4; 1079 return Result; 1080 } 1081 1082 uint32_t NEONv8Insn = Insn32; 1083 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1084 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1085 this, STI); 1086 if (Result != MCDisassembler::Fail) { 1087 Size = 4; 1088 return Result; 1089 } 1090 } 1091 1092 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4); 1093 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI) 1094 ? DecoderTableThumb2CDE32 1095 : DecoderTableThumb2CoProc32; 1096 Result = 1097 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI); 1098 if (Result != MCDisassembler::Fail) { 1099 Size = 4; 1100 Check(Result, AddThumbPredicate(MI)); 1101 return Result; 1102 } 1103 1104 Size = 0; 1105 return MCDisassembler::Fail; 1106 } 1107 1108 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() { 1109 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1110 createARMDisassembler); 1111 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1112 createARMDisassembler); 1113 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1114 createARMDisassembler); 1115 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1116 createARMDisassembler); 1117 } 1118 1119 static const uint16_t GPRDecoderTable[] = { 1120 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1121 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1122 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1123 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1124 }; 1125 1126 static const uint16_t CLRMGPRDecoderTable[] = { 1127 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1128 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1129 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1130 ARM::R12, 0, ARM::LR, ARM::APSR 1131 }; 1132 1133 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1134 uint64_t Address, const void *Decoder) { 1135 if (RegNo > 15) 1136 return MCDisassembler::Fail; 1137 1138 unsigned Register = GPRDecoderTable[RegNo]; 1139 Inst.addOperand(MCOperand::createReg(Register)); 1140 return MCDisassembler::Success; 1141 } 1142 1143 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1144 uint64_t Address, 1145 const void *Decoder) { 1146 if (RegNo > 15) 1147 return MCDisassembler::Fail; 1148 1149 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1150 if (Register == 0) 1151 return MCDisassembler::Fail; 1152 1153 Inst.addOperand(MCOperand::createReg(Register)); 1154 return MCDisassembler::Success; 1155 } 1156 1157 static DecodeStatus 1158 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1159 uint64_t Address, const void *Decoder) { 1160 DecodeStatus S = MCDisassembler::Success; 1161 1162 if (RegNo == 15) 1163 S = MCDisassembler::SoftFail; 1164 1165 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1166 1167 return S; 1168 } 1169 1170 static DecodeStatus 1171 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1172 uint64_t Address, const void *Decoder) { 1173 DecodeStatus S = MCDisassembler::Success; 1174 1175 if (RegNo == 15) 1176 { 1177 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1178 return MCDisassembler::Success; 1179 } 1180 1181 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1182 return S; 1183 } 1184 1185 static DecodeStatus 1186 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1187 uint64_t Address, const void *Decoder) { 1188 DecodeStatus S = MCDisassembler::Success; 1189 1190 if (RegNo == 15) 1191 { 1192 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1193 return MCDisassembler::Success; 1194 } 1195 1196 if (RegNo == 13) 1197 Check(S, MCDisassembler::SoftFail); 1198 1199 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1200 return S; 1201 } 1202 1203 static DecodeStatus 1204 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1205 uint64_t Address, const void *Decoder) { 1206 DecodeStatus S = MCDisassembler::Success; 1207 if (RegNo == 13) 1208 return MCDisassembler::Fail; 1209 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); 1210 return S; 1211 } 1212 1213 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1214 uint64_t Address, const void *Decoder) { 1215 if (RegNo > 7) 1216 return MCDisassembler::Fail; 1217 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1218 } 1219 1220 static const uint16_t GPRPairDecoderTable[] = { 1221 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1222 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1223 }; 1224 1225 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1226 uint64_t Address, const void *Decoder) { 1227 DecodeStatus S = MCDisassembler::Success; 1228 1229 // According to the Arm ARM RegNo = 14 is undefined, but we return fail 1230 // rather than SoftFail as there is no GPRPair table entry for index 7. 1231 if (RegNo > 13) 1232 return MCDisassembler::Fail; 1233 1234 if (RegNo & 1) 1235 S = MCDisassembler::SoftFail; 1236 1237 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1238 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1239 return S; 1240 } 1241 1242 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, 1243 uint64_t Address, const void *Decoder) { 1244 if (RegNo > 13) 1245 return MCDisassembler::Fail; 1246 1247 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1248 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1249 1250 if ((RegNo & 1) || RegNo > 10) 1251 return MCDisassembler::SoftFail; 1252 return MCDisassembler::Success; 1253 } 1254 1255 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 1256 uint64_t Address, 1257 const void *Decoder) { 1258 if (RegNo != 13) 1259 return MCDisassembler::Fail; 1260 1261 unsigned Register = GPRDecoderTable[RegNo]; 1262 Inst.addOperand(MCOperand::createReg(Register)); 1263 return MCDisassembler::Success; 1264 } 1265 1266 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1267 uint64_t Address, const void *Decoder) { 1268 unsigned Register = 0; 1269 switch (RegNo) { 1270 case 0: 1271 Register = ARM::R0; 1272 break; 1273 case 1: 1274 Register = ARM::R1; 1275 break; 1276 case 2: 1277 Register = ARM::R2; 1278 break; 1279 case 3: 1280 Register = ARM::R3; 1281 break; 1282 case 9: 1283 Register = ARM::R9; 1284 break; 1285 case 12: 1286 Register = ARM::R12; 1287 break; 1288 default: 1289 return MCDisassembler::Fail; 1290 } 1291 1292 Inst.addOperand(MCOperand::createReg(Register)); 1293 return MCDisassembler::Success; 1294 } 1295 1296 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1297 uint64_t Address, const void *Decoder) { 1298 DecodeStatus S = MCDisassembler::Success; 1299 1300 const FeatureBitset &featureBits = 1301 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1302 1303 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1304 S = MCDisassembler::SoftFail; 1305 1306 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1307 return S; 1308 } 1309 1310 static const uint16_t SPRDecoderTable[] = { 1311 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1312 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1313 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1314 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1315 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1316 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1317 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1318 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1319 }; 1320 1321 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1322 uint64_t Address, const void *Decoder) { 1323 if (RegNo > 31) 1324 return MCDisassembler::Fail; 1325 1326 unsigned Register = SPRDecoderTable[RegNo]; 1327 Inst.addOperand(MCOperand::createReg(Register)); 1328 return MCDisassembler::Success; 1329 } 1330 1331 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1332 uint64_t Address, const void *Decoder) { 1333 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1334 } 1335 1336 static const uint16_t DPRDecoderTable[] = { 1337 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1338 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1339 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1340 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1341 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1342 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1343 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1344 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1345 }; 1346 1347 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1348 uint64_t Address, const void *Decoder) { 1349 const FeatureBitset &featureBits = 1350 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1351 1352 bool hasD32 = featureBits[ARM::FeatureD32]; 1353 1354 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1355 return MCDisassembler::Fail; 1356 1357 unsigned Register = DPRDecoderTable[RegNo]; 1358 Inst.addOperand(MCOperand::createReg(Register)); 1359 return MCDisassembler::Success; 1360 } 1361 1362 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1363 uint64_t Address, const void *Decoder) { 1364 if (RegNo > 7) 1365 return MCDisassembler::Fail; 1366 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1367 } 1368 1369 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1370 uint64_t Address, const void *Decoder) { 1371 if (RegNo > 15) 1372 return MCDisassembler::Fail; 1373 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1374 } 1375 1376 static DecodeStatus 1377 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1378 uint64_t Address, const void *Decoder) { 1379 if (RegNo > 15) 1380 return MCDisassembler::Fail; 1381 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1382 } 1383 1384 static const uint16_t QPRDecoderTable[] = { 1385 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1386 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1387 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1388 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1389 }; 1390 1391 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1392 uint64_t Address, const void *Decoder) { 1393 if (RegNo > 31 || (RegNo & 1) != 0) 1394 return MCDisassembler::Fail; 1395 RegNo >>= 1; 1396 1397 unsigned Register = QPRDecoderTable[RegNo]; 1398 Inst.addOperand(MCOperand::createReg(Register)); 1399 return MCDisassembler::Success; 1400 } 1401 1402 static const uint16_t DPairDecoderTable[] = { 1403 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1404 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1405 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1406 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1407 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1408 ARM::Q15 1409 }; 1410 1411 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1412 uint64_t Address, const void *Decoder) { 1413 if (RegNo > 30) 1414 return MCDisassembler::Fail; 1415 1416 unsigned Register = DPairDecoderTable[RegNo]; 1417 Inst.addOperand(MCOperand::createReg(Register)); 1418 return MCDisassembler::Success; 1419 } 1420 1421 static const uint16_t DPairSpacedDecoderTable[] = { 1422 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1423 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1424 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1425 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1426 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1427 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1428 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1429 ARM::D28_D30, ARM::D29_D31 1430 }; 1431 1432 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1433 unsigned RegNo, 1434 uint64_t Address, 1435 const void *Decoder) { 1436 if (RegNo > 29) 1437 return MCDisassembler::Fail; 1438 1439 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1440 Inst.addOperand(MCOperand::createReg(Register)); 1441 return MCDisassembler::Success; 1442 } 1443 1444 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1445 uint64_t Address, const void *Decoder) { 1446 DecodeStatus S = MCDisassembler::Success; 1447 if (Val == 0xF) return MCDisassembler::Fail; 1448 // AL predicate is not allowed on Thumb1 branches. 1449 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1450 return MCDisassembler::Fail; 1451 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1452 Check(S, MCDisassembler::SoftFail); 1453 Inst.addOperand(MCOperand::createImm(Val)); 1454 if (Val == ARMCC::AL) { 1455 Inst.addOperand(MCOperand::createReg(0)); 1456 } else 1457 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1458 return S; 1459 } 1460 1461 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1462 uint64_t Address, const void *Decoder) { 1463 if (Val) 1464 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1465 else 1466 Inst.addOperand(MCOperand::createReg(0)); 1467 return MCDisassembler::Success; 1468 } 1469 1470 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1471 uint64_t Address, const void *Decoder) { 1472 DecodeStatus S = MCDisassembler::Success; 1473 1474 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1475 unsigned type = fieldFromInstruction(Val, 5, 2); 1476 unsigned imm = fieldFromInstruction(Val, 7, 5); 1477 1478 // Register-immediate 1479 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1480 return MCDisassembler::Fail; 1481 1482 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1483 switch (type) { 1484 case 0: 1485 Shift = ARM_AM::lsl; 1486 break; 1487 case 1: 1488 Shift = ARM_AM::lsr; 1489 break; 1490 case 2: 1491 Shift = ARM_AM::asr; 1492 break; 1493 case 3: 1494 Shift = ARM_AM::ror; 1495 break; 1496 } 1497 1498 if (Shift == ARM_AM::ror && imm == 0) 1499 Shift = ARM_AM::rrx; 1500 1501 unsigned Op = Shift | (imm << 3); 1502 Inst.addOperand(MCOperand::createImm(Op)); 1503 1504 return S; 1505 } 1506 1507 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1508 uint64_t Address, const void *Decoder) { 1509 DecodeStatus S = MCDisassembler::Success; 1510 1511 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1512 unsigned type = fieldFromInstruction(Val, 5, 2); 1513 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1514 1515 // Register-register 1516 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1517 return MCDisassembler::Fail; 1518 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1519 return MCDisassembler::Fail; 1520 1521 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1522 switch (type) { 1523 case 0: 1524 Shift = ARM_AM::lsl; 1525 break; 1526 case 1: 1527 Shift = ARM_AM::lsr; 1528 break; 1529 case 2: 1530 Shift = ARM_AM::asr; 1531 break; 1532 case 3: 1533 Shift = ARM_AM::ror; 1534 break; 1535 } 1536 1537 Inst.addOperand(MCOperand::createImm(Shift)); 1538 1539 return S; 1540 } 1541 1542 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1543 uint64_t Address, const void *Decoder) { 1544 DecodeStatus S = MCDisassembler::Success; 1545 1546 bool NeedDisjointWriteback = false; 1547 unsigned WritebackReg = 0; 1548 bool CLRM = false; 1549 switch (Inst.getOpcode()) { 1550 default: 1551 break; 1552 case ARM::LDMIA_UPD: 1553 case ARM::LDMDB_UPD: 1554 case ARM::LDMIB_UPD: 1555 case ARM::LDMDA_UPD: 1556 case ARM::t2LDMIA_UPD: 1557 case ARM::t2LDMDB_UPD: 1558 case ARM::t2STMIA_UPD: 1559 case ARM::t2STMDB_UPD: 1560 NeedDisjointWriteback = true; 1561 WritebackReg = Inst.getOperand(0).getReg(); 1562 break; 1563 case ARM::t2CLRM: 1564 CLRM = true; 1565 break; 1566 } 1567 1568 // Empty register lists are not allowed. 1569 if (Val == 0) return MCDisassembler::Fail; 1570 for (unsigned i = 0; i < 16; ++i) { 1571 if (Val & (1 << i)) { 1572 if (CLRM) { 1573 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1574 return MCDisassembler::Fail; 1575 } 1576 } else { 1577 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1578 return MCDisassembler::Fail; 1579 // Writeback not allowed if Rn is in the target list. 1580 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1581 Check(S, MCDisassembler::SoftFail); 1582 } 1583 } 1584 } 1585 1586 return S; 1587 } 1588 1589 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1590 uint64_t Address, const void *Decoder) { 1591 DecodeStatus S = MCDisassembler::Success; 1592 1593 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1594 unsigned regs = fieldFromInstruction(Val, 0, 8); 1595 1596 // In case of unpredictable encoding, tweak the operands. 1597 if (regs == 0 || (Vd + regs) > 32) { 1598 regs = Vd + regs > 32 ? 32 - Vd : regs; 1599 regs = std::max( 1u, regs); 1600 S = MCDisassembler::SoftFail; 1601 } 1602 1603 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1604 return MCDisassembler::Fail; 1605 for (unsigned i = 0; i < (regs - 1); ++i) { 1606 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1607 return MCDisassembler::Fail; 1608 } 1609 1610 return S; 1611 } 1612 1613 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1614 uint64_t Address, const void *Decoder) { 1615 DecodeStatus S = MCDisassembler::Success; 1616 1617 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1618 unsigned regs = fieldFromInstruction(Val, 1, 7); 1619 1620 // In case of unpredictable encoding, tweak the operands. 1621 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1622 regs = Vd + regs > 32 ? 32 - Vd : regs; 1623 regs = std::max( 1u, regs); 1624 regs = std::min(16u, regs); 1625 S = MCDisassembler::SoftFail; 1626 } 1627 1628 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1629 return MCDisassembler::Fail; 1630 for (unsigned i = 0; i < (regs - 1); ++i) { 1631 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1632 return MCDisassembler::Fail; 1633 } 1634 1635 return S; 1636 } 1637 1638 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1639 uint64_t Address, const void *Decoder) { 1640 // This operand encodes a mask of contiguous zeros between a specified MSB 1641 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1642 // the mask of all bits LSB-and-lower, and then xor them to create 1643 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1644 // create the final mask. 1645 unsigned msb = fieldFromInstruction(Val, 5, 5); 1646 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1647 1648 DecodeStatus S = MCDisassembler::Success; 1649 if (lsb > msb) { 1650 Check(S, MCDisassembler::SoftFail); 1651 // The check above will cause the warning for the "potentially undefined 1652 // instruction encoding" but we can't build a bad MCOperand value here 1653 // with a lsb > msb or else printing the MCInst will cause a crash. 1654 lsb = msb; 1655 } 1656 1657 uint32_t msb_mask = 0xFFFFFFFF; 1658 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1659 uint32_t lsb_mask = (1U << lsb) - 1; 1660 1661 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1662 return S; 1663 } 1664 1665 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1666 uint64_t Address, const void *Decoder) { 1667 DecodeStatus S = MCDisassembler::Success; 1668 1669 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1670 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1671 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1672 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1673 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1674 unsigned U = fieldFromInstruction(Insn, 23, 1); 1675 const FeatureBitset &featureBits = 1676 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1677 1678 switch (Inst.getOpcode()) { 1679 case ARM::LDC_OFFSET: 1680 case ARM::LDC_PRE: 1681 case ARM::LDC_POST: 1682 case ARM::LDC_OPTION: 1683 case ARM::LDCL_OFFSET: 1684 case ARM::LDCL_PRE: 1685 case ARM::LDCL_POST: 1686 case ARM::LDCL_OPTION: 1687 case ARM::STC_OFFSET: 1688 case ARM::STC_PRE: 1689 case ARM::STC_POST: 1690 case ARM::STC_OPTION: 1691 case ARM::STCL_OFFSET: 1692 case ARM::STCL_PRE: 1693 case ARM::STCL_POST: 1694 case ARM::STCL_OPTION: 1695 case ARM::t2LDC_OFFSET: 1696 case ARM::t2LDC_PRE: 1697 case ARM::t2LDC_POST: 1698 case ARM::t2LDC_OPTION: 1699 case ARM::t2LDCL_OFFSET: 1700 case ARM::t2LDCL_PRE: 1701 case ARM::t2LDCL_POST: 1702 case ARM::t2LDCL_OPTION: 1703 case ARM::t2STC_OFFSET: 1704 case ARM::t2STC_PRE: 1705 case ARM::t2STC_POST: 1706 case ARM::t2STC_OPTION: 1707 case ARM::t2STCL_OFFSET: 1708 case ARM::t2STCL_PRE: 1709 case ARM::t2STCL_POST: 1710 case ARM::t2STCL_OPTION: 1711 case ARM::t2LDC2_OFFSET: 1712 case ARM::t2LDC2L_OFFSET: 1713 case ARM::t2LDC2_PRE: 1714 case ARM::t2LDC2L_PRE: 1715 case ARM::t2STC2_OFFSET: 1716 case ARM::t2STC2L_OFFSET: 1717 case ARM::t2STC2_PRE: 1718 case ARM::t2STC2L_PRE: 1719 case ARM::LDC2_OFFSET: 1720 case ARM::LDC2L_OFFSET: 1721 case ARM::LDC2_PRE: 1722 case ARM::LDC2L_PRE: 1723 case ARM::STC2_OFFSET: 1724 case ARM::STC2L_OFFSET: 1725 case ARM::STC2_PRE: 1726 case ARM::STC2L_PRE: 1727 case ARM::t2LDC2_OPTION: 1728 case ARM::t2STC2_OPTION: 1729 case ARM::t2LDC2_POST: 1730 case ARM::t2LDC2L_POST: 1731 case ARM::t2STC2_POST: 1732 case ARM::t2STC2L_POST: 1733 case ARM::LDC2_POST: 1734 case ARM::LDC2L_POST: 1735 case ARM::STC2_POST: 1736 case ARM::STC2L_POST: 1737 if (coproc == 0xA || coproc == 0xB || 1738 (featureBits[ARM::HasV8_1MMainlineOps] && 1739 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1740 coproc == 0xE || coproc == 0xF))) 1741 return MCDisassembler::Fail; 1742 break; 1743 default: 1744 break; 1745 } 1746 1747 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1748 return MCDisassembler::Fail; 1749 1750 Inst.addOperand(MCOperand::createImm(coproc)); 1751 Inst.addOperand(MCOperand::createImm(CRd)); 1752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1753 return MCDisassembler::Fail; 1754 1755 switch (Inst.getOpcode()) { 1756 case ARM::t2LDC2_OFFSET: 1757 case ARM::t2LDC2L_OFFSET: 1758 case ARM::t2LDC2_PRE: 1759 case ARM::t2LDC2L_PRE: 1760 case ARM::t2STC2_OFFSET: 1761 case ARM::t2STC2L_OFFSET: 1762 case ARM::t2STC2_PRE: 1763 case ARM::t2STC2L_PRE: 1764 case ARM::LDC2_OFFSET: 1765 case ARM::LDC2L_OFFSET: 1766 case ARM::LDC2_PRE: 1767 case ARM::LDC2L_PRE: 1768 case ARM::STC2_OFFSET: 1769 case ARM::STC2L_OFFSET: 1770 case ARM::STC2_PRE: 1771 case ARM::STC2L_PRE: 1772 case ARM::t2LDC_OFFSET: 1773 case ARM::t2LDCL_OFFSET: 1774 case ARM::t2LDC_PRE: 1775 case ARM::t2LDCL_PRE: 1776 case ARM::t2STC_OFFSET: 1777 case ARM::t2STCL_OFFSET: 1778 case ARM::t2STC_PRE: 1779 case ARM::t2STCL_PRE: 1780 case ARM::LDC_OFFSET: 1781 case ARM::LDCL_OFFSET: 1782 case ARM::LDC_PRE: 1783 case ARM::LDCL_PRE: 1784 case ARM::STC_OFFSET: 1785 case ARM::STCL_OFFSET: 1786 case ARM::STC_PRE: 1787 case ARM::STCL_PRE: 1788 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1789 Inst.addOperand(MCOperand::createImm(imm)); 1790 break; 1791 case ARM::t2LDC2_POST: 1792 case ARM::t2LDC2L_POST: 1793 case ARM::t2STC2_POST: 1794 case ARM::t2STC2L_POST: 1795 case ARM::LDC2_POST: 1796 case ARM::LDC2L_POST: 1797 case ARM::STC2_POST: 1798 case ARM::STC2L_POST: 1799 case ARM::t2LDC_POST: 1800 case ARM::t2LDCL_POST: 1801 case ARM::t2STC_POST: 1802 case ARM::t2STCL_POST: 1803 case ARM::LDC_POST: 1804 case ARM::LDCL_POST: 1805 case ARM::STC_POST: 1806 case ARM::STCL_POST: 1807 imm |= U << 8; 1808 LLVM_FALLTHROUGH; 1809 default: 1810 // The 'option' variant doesn't encode 'U' in the immediate since 1811 // the immediate is unsigned [0,255]. 1812 Inst.addOperand(MCOperand::createImm(imm)); 1813 break; 1814 } 1815 1816 switch (Inst.getOpcode()) { 1817 case ARM::LDC_OFFSET: 1818 case ARM::LDC_PRE: 1819 case ARM::LDC_POST: 1820 case ARM::LDC_OPTION: 1821 case ARM::LDCL_OFFSET: 1822 case ARM::LDCL_PRE: 1823 case ARM::LDCL_POST: 1824 case ARM::LDCL_OPTION: 1825 case ARM::STC_OFFSET: 1826 case ARM::STC_PRE: 1827 case ARM::STC_POST: 1828 case ARM::STC_OPTION: 1829 case ARM::STCL_OFFSET: 1830 case ARM::STCL_PRE: 1831 case ARM::STCL_POST: 1832 case ARM::STCL_OPTION: 1833 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1834 return MCDisassembler::Fail; 1835 break; 1836 default: 1837 break; 1838 } 1839 1840 return S; 1841 } 1842 1843 static DecodeStatus 1844 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1845 uint64_t Address, const void *Decoder) { 1846 DecodeStatus S = MCDisassembler::Success; 1847 1848 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1849 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1850 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1851 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1852 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1853 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1854 unsigned P = fieldFromInstruction(Insn, 24, 1); 1855 unsigned W = fieldFromInstruction(Insn, 21, 1); 1856 1857 // On stores, the writeback operand precedes Rt. 1858 switch (Inst.getOpcode()) { 1859 case ARM::STR_POST_IMM: 1860 case ARM::STR_POST_REG: 1861 case ARM::STRB_POST_IMM: 1862 case ARM::STRB_POST_REG: 1863 case ARM::STRT_POST_REG: 1864 case ARM::STRT_POST_IMM: 1865 case ARM::STRBT_POST_REG: 1866 case ARM::STRBT_POST_IMM: 1867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1868 return MCDisassembler::Fail; 1869 break; 1870 default: 1871 break; 1872 } 1873 1874 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1875 return MCDisassembler::Fail; 1876 1877 // On loads, the writeback operand comes after Rt. 1878 switch (Inst.getOpcode()) { 1879 case ARM::LDR_POST_IMM: 1880 case ARM::LDR_POST_REG: 1881 case ARM::LDRB_POST_IMM: 1882 case ARM::LDRB_POST_REG: 1883 case ARM::LDRBT_POST_REG: 1884 case ARM::LDRBT_POST_IMM: 1885 case ARM::LDRT_POST_REG: 1886 case ARM::LDRT_POST_IMM: 1887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1888 return MCDisassembler::Fail; 1889 break; 1890 default: 1891 break; 1892 } 1893 1894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1895 return MCDisassembler::Fail; 1896 1897 ARM_AM::AddrOpc Op = ARM_AM::add; 1898 if (!fieldFromInstruction(Insn, 23, 1)) 1899 Op = ARM_AM::sub; 1900 1901 bool writeback = (P == 0) || (W == 1); 1902 unsigned idx_mode = 0; 1903 if (P && writeback) 1904 idx_mode = ARMII::IndexModePre; 1905 else if (!P && writeback) 1906 idx_mode = ARMII::IndexModePost; 1907 1908 if (writeback && (Rn == 15 || Rn == Rt)) 1909 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1910 1911 if (reg) { 1912 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1913 return MCDisassembler::Fail; 1914 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1915 switch( fieldFromInstruction(Insn, 5, 2)) { 1916 case 0: 1917 Opc = ARM_AM::lsl; 1918 break; 1919 case 1: 1920 Opc = ARM_AM::lsr; 1921 break; 1922 case 2: 1923 Opc = ARM_AM::asr; 1924 break; 1925 case 3: 1926 Opc = ARM_AM::ror; 1927 break; 1928 default: 1929 return MCDisassembler::Fail; 1930 } 1931 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1932 if (Opc == ARM_AM::ror && amt == 0) 1933 Opc = ARM_AM::rrx; 1934 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1935 1936 Inst.addOperand(MCOperand::createImm(imm)); 1937 } else { 1938 Inst.addOperand(MCOperand::createReg(0)); 1939 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1940 Inst.addOperand(MCOperand::createImm(tmp)); 1941 } 1942 1943 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1944 return MCDisassembler::Fail; 1945 1946 return S; 1947 } 1948 1949 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1950 uint64_t Address, const void *Decoder) { 1951 DecodeStatus S = MCDisassembler::Success; 1952 1953 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1954 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1955 unsigned type = fieldFromInstruction(Val, 5, 2); 1956 unsigned imm = fieldFromInstruction(Val, 7, 5); 1957 unsigned U = fieldFromInstruction(Val, 12, 1); 1958 1959 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1960 switch (type) { 1961 case 0: 1962 ShOp = ARM_AM::lsl; 1963 break; 1964 case 1: 1965 ShOp = ARM_AM::lsr; 1966 break; 1967 case 2: 1968 ShOp = ARM_AM::asr; 1969 break; 1970 case 3: 1971 ShOp = ARM_AM::ror; 1972 break; 1973 } 1974 1975 if (ShOp == ARM_AM::ror && imm == 0) 1976 ShOp = ARM_AM::rrx; 1977 1978 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1979 return MCDisassembler::Fail; 1980 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1981 return MCDisassembler::Fail; 1982 unsigned shift; 1983 if (U) 1984 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1985 else 1986 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1987 Inst.addOperand(MCOperand::createImm(shift)); 1988 1989 return S; 1990 } 1991 1992 static DecodeStatus 1993 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1994 uint64_t Address, const void *Decoder) { 1995 DecodeStatus S = MCDisassembler::Success; 1996 1997 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1998 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1999 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2000 unsigned type = fieldFromInstruction(Insn, 22, 1); 2001 unsigned imm = fieldFromInstruction(Insn, 8, 4); 2002 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 2003 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2004 unsigned W = fieldFromInstruction(Insn, 21, 1); 2005 unsigned P = fieldFromInstruction(Insn, 24, 1); 2006 unsigned Rt2 = Rt + 1; 2007 2008 bool writeback = (W == 1) | (P == 0); 2009 2010 // For {LD,ST}RD, Rt must be even, else undefined. 2011 switch (Inst.getOpcode()) { 2012 case ARM::STRD: 2013 case ARM::STRD_PRE: 2014 case ARM::STRD_POST: 2015 case ARM::LDRD: 2016 case ARM::LDRD_PRE: 2017 case ARM::LDRD_POST: 2018 if (Rt & 0x1) S = MCDisassembler::SoftFail; 2019 break; 2020 default: 2021 break; 2022 } 2023 switch (Inst.getOpcode()) { 2024 case ARM::STRD: 2025 case ARM::STRD_PRE: 2026 case ARM::STRD_POST: 2027 if (P == 0 && W == 1) 2028 S = MCDisassembler::SoftFail; 2029 2030 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 2031 S = MCDisassembler::SoftFail; 2032 if (type && Rm == 15) 2033 S = MCDisassembler::SoftFail; 2034 if (Rt2 == 15) 2035 S = MCDisassembler::SoftFail; 2036 if (!type && fieldFromInstruction(Insn, 8, 4)) 2037 S = MCDisassembler::SoftFail; 2038 break; 2039 case ARM::STRH: 2040 case ARM::STRH_PRE: 2041 case ARM::STRH_POST: 2042 if (Rt == 15) 2043 S = MCDisassembler::SoftFail; 2044 if (writeback && (Rn == 15 || Rn == Rt)) 2045 S = MCDisassembler::SoftFail; 2046 if (!type && Rm == 15) 2047 S = MCDisassembler::SoftFail; 2048 break; 2049 case ARM::LDRD: 2050 case ARM::LDRD_PRE: 2051 case ARM::LDRD_POST: 2052 if (type && Rn == 15) { 2053 if (Rt2 == 15) 2054 S = MCDisassembler::SoftFail; 2055 break; 2056 } 2057 if (P == 0 && W == 1) 2058 S = MCDisassembler::SoftFail; 2059 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2060 S = MCDisassembler::SoftFail; 2061 if (!type && writeback && Rn == 15) 2062 S = MCDisassembler::SoftFail; 2063 if (writeback && (Rn == Rt || Rn == Rt2)) 2064 S = MCDisassembler::SoftFail; 2065 break; 2066 case ARM::LDRH: 2067 case ARM::LDRH_PRE: 2068 case ARM::LDRH_POST: 2069 if (type && Rn == 15) { 2070 if (Rt == 15) 2071 S = MCDisassembler::SoftFail; 2072 break; 2073 } 2074 if (Rt == 15) 2075 S = MCDisassembler::SoftFail; 2076 if (!type && Rm == 15) 2077 S = MCDisassembler::SoftFail; 2078 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2079 S = MCDisassembler::SoftFail; 2080 break; 2081 case ARM::LDRSH: 2082 case ARM::LDRSH_PRE: 2083 case ARM::LDRSH_POST: 2084 case ARM::LDRSB: 2085 case ARM::LDRSB_PRE: 2086 case ARM::LDRSB_POST: 2087 if (type && Rn == 15) { 2088 if (Rt == 15) 2089 S = MCDisassembler::SoftFail; 2090 break; 2091 } 2092 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2093 S = MCDisassembler::SoftFail; 2094 if (!type && (Rt == 15 || Rm == 15)) 2095 S = MCDisassembler::SoftFail; 2096 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2097 S = MCDisassembler::SoftFail; 2098 break; 2099 default: 2100 break; 2101 } 2102 2103 if (writeback) { // Writeback 2104 if (P) 2105 U |= ARMII::IndexModePre << 9; 2106 else 2107 U |= ARMII::IndexModePost << 9; 2108 2109 // On stores, the writeback operand precedes Rt. 2110 switch (Inst.getOpcode()) { 2111 case ARM::STRD: 2112 case ARM::STRD_PRE: 2113 case ARM::STRD_POST: 2114 case ARM::STRH: 2115 case ARM::STRH_PRE: 2116 case ARM::STRH_POST: 2117 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2118 return MCDisassembler::Fail; 2119 break; 2120 default: 2121 break; 2122 } 2123 } 2124 2125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2126 return MCDisassembler::Fail; 2127 switch (Inst.getOpcode()) { 2128 case ARM::STRD: 2129 case ARM::STRD_PRE: 2130 case ARM::STRD_POST: 2131 case ARM::LDRD: 2132 case ARM::LDRD_PRE: 2133 case ARM::LDRD_POST: 2134 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2135 return MCDisassembler::Fail; 2136 break; 2137 default: 2138 break; 2139 } 2140 2141 if (writeback) { 2142 // On loads, the writeback operand comes after Rt. 2143 switch (Inst.getOpcode()) { 2144 case ARM::LDRD: 2145 case ARM::LDRD_PRE: 2146 case ARM::LDRD_POST: 2147 case ARM::LDRH: 2148 case ARM::LDRH_PRE: 2149 case ARM::LDRH_POST: 2150 case ARM::LDRSH: 2151 case ARM::LDRSH_PRE: 2152 case ARM::LDRSH_POST: 2153 case ARM::LDRSB: 2154 case ARM::LDRSB_PRE: 2155 case ARM::LDRSB_POST: 2156 case ARM::LDRHTr: 2157 case ARM::LDRSBTr: 2158 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2159 return MCDisassembler::Fail; 2160 break; 2161 default: 2162 break; 2163 } 2164 } 2165 2166 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2167 return MCDisassembler::Fail; 2168 2169 if (type) { 2170 Inst.addOperand(MCOperand::createReg(0)); 2171 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2172 } else { 2173 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2174 return MCDisassembler::Fail; 2175 Inst.addOperand(MCOperand::createImm(U)); 2176 } 2177 2178 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2179 return MCDisassembler::Fail; 2180 2181 return S; 2182 } 2183 2184 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2185 uint64_t Address, const void *Decoder) { 2186 DecodeStatus S = MCDisassembler::Success; 2187 2188 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2189 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2190 2191 switch (mode) { 2192 case 0: 2193 mode = ARM_AM::da; 2194 break; 2195 case 1: 2196 mode = ARM_AM::ia; 2197 break; 2198 case 2: 2199 mode = ARM_AM::db; 2200 break; 2201 case 3: 2202 mode = ARM_AM::ib; 2203 break; 2204 } 2205 2206 Inst.addOperand(MCOperand::createImm(mode)); 2207 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2208 return MCDisassembler::Fail; 2209 2210 return S; 2211 } 2212 2213 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2214 uint64_t Address, const void *Decoder) { 2215 DecodeStatus S = MCDisassembler::Success; 2216 2217 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2218 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2219 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2220 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2221 2222 if (pred == 0xF) 2223 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2224 2225 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2226 return MCDisassembler::Fail; 2227 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2228 return MCDisassembler::Fail; 2229 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2230 return MCDisassembler::Fail; 2231 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2232 return MCDisassembler::Fail; 2233 return S; 2234 } 2235 2236 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2237 unsigned Insn, 2238 uint64_t Address, const void *Decoder) { 2239 DecodeStatus S = MCDisassembler::Success; 2240 2241 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2242 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2243 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2244 2245 if (pred == 0xF) { 2246 // Ambiguous with RFE and SRS 2247 switch (Inst.getOpcode()) { 2248 case ARM::LDMDA: 2249 Inst.setOpcode(ARM::RFEDA); 2250 break; 2251 case ARM::LDMDA_UPD: 2252 Inst.setOpcode(ARM::RFEDA_UPD); 2253 break; 2254 case ARM::LDMDB: 2255 Inst.setOpcode(ARM::RFEDB); 2256 break; 2257 case ARM::LDMDB_UPD: 2258 Inst.setOpcode(ARM::RFEDB_UPD); 2259 break; 2260 case ARM::LDMIA: 2261 Inst.setOpcode(ARM::RFEIA); 2262 break; 2263 case ARM::LDMIA_UPD: 2264 Inst.setOpcode(ARM::RFEIA_UPD); 2265 break; 2266 case ARM::LDMIB: 2267 Inst.setOpcode(ARM::RFEIB); 2268 break; 2269 case ARM::LDMIB_UPD: 2270 Inst.setOpcode(ARM::RFEIB_UPD); 2271 break; 2272 case ARM::STMDA: 2273 Inst.setOpcode(ARM::SRSDA); 2274 break; 2275 case ARM::STMDA_UPD: 2276 Inst.setOpcode(ARM::SRSDA_UPD); 2277 break; 2278 case ARM::STMDB: 2279 Inst.setOpcode(ARM::SRSDB); 2280 break; 2281 case ARM::STMDB_UPD: 2282 Inst.setOpcode(ARM::SRSDB_UPD); 2283 break; 2284 case ARM::STMIA: 2285 Inst.setOpcode(ARM::SRSIA); 2286 break; 2287 case ARM::STMIA_UPD: 2288 Inst.setOpcode(ARM::SRSIA_UPD); 2289 break; 2290 case ARM::STMIB: 2291 Inst.setOpcode(ARM::SRSIB); 2292 break; 2293 case ARM::STMIB_UPD: 2294 Inst.setOpcode(ARM::SRSIB_UPD); 2295 break; 2296 default: 2297 return MCDisassembler::Fail; 2298 } 2299 2300 // For stores (which become SRS's, the only operand is the mode. 2301 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2302 // Check SRS encoding constraints 2303 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2304 fieldFromInstruction(Insn, 20, 1) == 0)) 2305 return MCDisassembler::Fail; 2306 2307 Inst.addOperand( 2308 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2309 return S; 2310 } 2311 2312 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2313 } 2314 2315 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2316 return MCDisassembler::Fail; 2317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2318 return MCDisassembler::Fail; // Tied 2319 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2320 return MCDisassembler::Fail; 2321 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2322 return MCDisassembler::Fail; 2323 2324 return S; 2325 } 2326 2327 // Check for UNPREDICTABLE predicated ESB instruction 2328 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2329 uint64_t Address, const void *Decoder) { 2330 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2331 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2332 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2333 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2334 2335 DecodeStatus S = MCDisassembler::Success; 2336 2337 Inst.addOperand(MCOperand::createImm(imm8)); 2338 2339 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2340 return MCDisassembler::Fail; 2341 2342 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2343 // so all predicates should be allowed. 2344 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2345 S = MCDisassembler::SoftFail; 2346 2347 return S; 2348 } 2349 2350 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2351 uint64_t Address, const void *Decoder) { 2352 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2353 unsigned M = fieldFromInstruction(Insn, 17, 1); 2354 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2355 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2356 2357 DecodeStatus S = MCDisassembler::Success; 2358 2359 // This decoder is called from multiple location that do not check 2360 // the full encoding is valid before they do. 2361 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2362 fieldFromInstruction(Insn, 16, 1) != 0 || 2363 fieldFromInstruction(Insn, 20, 8) != 0x10) 2364 return MCDisassembler::Fail; 2365 2366 // imod == '01' --> UNPREDICTABLE 2367 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2368 // return failure here. The '01' imod value is unprintable, so there's 2369 // nothing useful we could do even if we returned UNPREDICTABLE. 2370 2371 if (imod == 1) return MCDisassembler::Fail; 2372 2373 if (imod && M) { 2374 Inst.setOpcode(ARM::CPS3p); 2375 Inst.addOperand(MCOperand::createImm(imod)); 2376 Inst.addOperand(MCOperand::createImm(iflags)); 2377 Inst.addOperand(MCOperand::createImm(mode)); 2378 } else if (imod && !M) { 2379 Inst.setOpcode(ARM::CPS2p); 2380 Inst.addOperand(MCOperand::createImm(imod)); 2381 Inst.addOperand(MCOperand::createImm(iflags)); 2382 if (mode) S = MCDisassembler::SoftFail; 2383 } else if (!imod && M) { 2384 Inst.setOpcode(ARM::CPS1p); 2385 Inst.addOperand(MCOperand::createImm(mode)); 2386 if (iflags) S = MCDisassembler::SoftFail; 2387 } else { 2388 // imod == '00' && M == '0' --> UNPREDICTABLE 2389 Inst.setOpcode(ARM::CPS1p); 2390 Inst.addOperand(MCOperand::createImm(mode)); 2391 S = MCDisassembler::SoftFail; 2392 } 2393 2394 return S; 2395 } 2396 2397 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2398 uint64_t Address, const void *Decoder) { 2399 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2400 unsigned M = fieldFromInstruction(Insn, 8, 1); 2401 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2402 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2403 2404 DecodeStatus S = MCDisassembler::Success; 2405 2406 // imod == '01' --> UNPREDICTABLE 2407 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2408 // return failure here. The '01' imod value is unprintable, so there's 2409 // nothing useful we could do even if we returned UNPREDICTABLE. 2410 2411 if (imod == 1) return MCDisassembler::Fail; 2412 2413 if (imod && M) { 2414 Inst.setOpcode(ARM::t2CPS3p); 2415 Inst.addOperand(MCOperand::createImm(imod)); 2416 Inst.addOperand(MCOperand::createImm(iflags)); 2417 Inst.addOperand(MCOperand::createImm(mode)); 2418 } else if (imod && !M) { 2419 Inst.setOpcode(ARM::t2CPS2p); 2420 Inst.addOperand(MCOperand::createImm(imod)); 2421 Inst.addOperand(MCOperand::createImm(iflags)); 2422 if (mode) S = MCDisassembler::SoftFail; 2423 } else if (!imod && M) { 2424 Inst.setOpcode(ARM::t2CPS1p); 2425 Inst.addOperand(MCOperand::createImm(mode)); 2426 if (iflags) S = MCDisassembler::SoftFail; 2427 } else { 2428 // imod == '00' && M == '0' --> this is a HINT instruction 2429 int imm = fieldFromInstruction(Insn, 0, 8); 2430 // HINT are defined only for immediate in [0..4] 2431 if(imm > 4) return MCDisassembler::Fail; 2432 Inst.setOpcode(ARM::t2HINT); 2433 Inst.addOperand(MCOperand::createImm(imm)); 2434 } 2435 2436 return S; 2437 } 2438 2439 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2440 uint64_t Address, const void *Decoder) { 2441 DecodeStatus S = MCDisassembler::Success; 2442 2443 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2444 unsigned imm = 0; 2445 2446 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2447 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2448 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2449 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2450 2451 if (Inst.getOpcode() == ARM::t2MOVTi16) 2452 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2453 return MCDisassembler::Fail; 2454 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2455 return MCDisassembler::Fail; 2456 2457 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2458 Inst.addOperand(MCOperand::createImm(imm)); 2459 2460 return S; 2461 } 2462 2463 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2464 uint64_t Address, const void *Decoder) { 2465 DecodeStatus S = MCDisassembler::Success; 2466 2467 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2468 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2469 unsigned imm = 0; 2470 2471 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2472 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2473 2474 if (Inst.getOpcode() == ARM::MOVTi16) 2475 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2476 return MCDisassembler::Fail; 2477 2478 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2479 return MCDisassembler::Fail; 2480 2481 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2482 Inst.addOperand(MCOperand::createImm(imm)); 2483 2484 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2485 return MCDisassembler::Fail; 2486 2487 return S; 2488 } 2489 2490 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2491 uint64_t Address, const void *Decoder) { 2492 DecodeStatus S = MCDisassembler::Success; 2493 2494 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2495 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2496 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2497 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2498 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2499 2500 if (pred == 0xF) 2501 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2502 2503 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2504 return MCDisassembler::Fail; 2505 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2506 return MCDisassembler::Fail; 2507 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2508 return MCDisassembler::Fail; 2509 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2510 return MCDisassembler::Fail; 2511 2512 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2513 return MCDisassembler::Fail; 2514 2515 return S; 2516 } 2517 2518 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2519 uint64_t Address, const void *Decoder) { 2520 DecodeStatus S = MCDisassembler::Success; 2521 2522 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2523 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2524 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2525 2526 if (Pred == 0xF) 2527 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2528 2529 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2530 return MCDisassembler::Fail; 2531 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2532 return MCDisassembler::Fail; 2533 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2534 return MCDisassembler::Fail; 2535 2536 return S; 2537 } 2538 2539 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2540 uint64_t Address, const void *Decoder) { 2541 DecodeStatus S = MCDisassembler::Success; 2542 2543 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2544 2545 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2546 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2547 2548 if (!FeatureBits[ARM::HasV8_1aOps] || 2549 !FeatureBits[ARM::HasV8Ops]) 2550 return MCDisassembler::Fail; 2551 2552 // Decoder can be called from DecodeTST, which does not check the full 2553 // encoding is valid. 2554 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2555 fieldFromInstruction(Insn, 4,4) != 0) 2556 return MCDisassembler::Fail; 2557 if (fieldFromInstruction(Insn, 10,10) != 0 || 2558 fieldFromInstruction(Insn, 0,4) != 0) 2559 S = MCDisassembler::SoftFail; 2560 2561 Inst.setOpcode(ARM::SETPAN); 2562 Inst.addOperand(MCOperand::createImm(Imm)); 2563 2564 return S; 2565 } 2566 2567 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2568 uint64_t Address, const void *Decoder) { 2569 DecodeStatus S = MCDisassembler::Success; 2570 2571 unsigned add = fieldFromInstruction(Val, 12, 1); 2572 unsigned imm = fieldFromInstruction(Val, 0, 12); 2573 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2574 2575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2576 return MCDisassembler::Fail; 2577 2578 if (!add) imm *= -1; 2579 if (imm == 0 && !add) imm = INT32_MIN; 2580 Inst.addOperand(MCOperand::createImm(imm)); 2581 if (Rn == 15) 2582 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2583 2584 return S; 2585 } 2586 2587 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2588 uint64_t Address, const void *Decoder) { 2589 DecodeStatus S = MCDisassembler::Success; 2590 2591 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2592 // U == 1 to add imm, 0 to subtract it. 2593 unsigned U = fieldFromInstruction(Val, 8, 1); 2594 unsigned imm = fieldFromInstruction(Val, 0, 8); 2595 2596 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2597 return MCDisassembler::Fail; 2598 2599 if (U) 2600 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2601 else 2602 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2603 2604 return S; 2605 } 2606 2607 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2608 uint64_t Address, const void *Decoder) { 2609 DecodeStatus S = MCDisassembler::Success; 2610 2611 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2612 // U == 1 to add imm, 0 to subtract it. 2613 unsigned U = fieldFromInstruction(Val, 8, 1); 2614 unsigned imm = fieldFromInstruction(Val, 0, 8); 2615 2616 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2617 return MCDisassembler::Fail; 2618 2619 if (U) 2620 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2621 else 2622 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2623 2624 return S; 2625 } 2626 2627 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2628 uint64_t Address, const void *Decoder) { 2629 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2630 } 2631 2632 static DecodeStatus 2633 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2634 uint64_t Address, const void *Decoder) { 2635 DecodeStatus Status = MCDisassembler::Success; 2636 2637 // Note the J1 and J2 values are from the encoded instruction. So here 2638 // change them to I1 and I2 values via as documented: 2639 // I1 = NOT(J1 EOR S); 2640 // I2 = NOT(J2 EOR S); 2641 // and build the imm32 with one trailing zero as documented: 2642 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2643 unsigned S = fieldFromInstruction(Insn, 26, 1); 2644 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2645 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2646 unsigned I1 = !(J1 ^ S); 2647 unsigned I2 = !(J2 ^ S); 2648 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2649 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2650 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2651 int imm32 = SignExtend32<25>(tmp << 1); 2652 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2653 true, 4, Inst, Decoder)) 2654 Inst.addOperand(MCOperand::createImm(imm32)); 2655 2656 return Status; 2657 } 2658 2659 static DecodeStatus 2660 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2661 uint64_t Address, const void *Decoder) { 2662 DecodeStatus S = MCDisassembler::Success; 2663 2664 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2665 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2666 2667 if (pred == 0xF) { 2668 Inst.setOpcode(ARM::BLXi); 2669 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2670 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2671 true, 4, Inst, Decoder)) 2672 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2673 return S; 2674 } 2675 2676 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2677 true, 4, Inst, Decoder)) 2678 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2679 2680 // We already have BL_pred for BL w/ predicate, no need to add addition 2681 // predicate opreands for BL 2682 if (Inst.getOpcode() != ARM::BL) 2683 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2684 return MCDisassembler::Fail; 2685 2686 return S; 2687 } 2688 2689 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2690 uint64_t Address, const void *Decoder) { 2691 DecodeStatus S = MCDisassembler::Success; 2692 2693 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2694 unsigned align = fieldFromInstruction(Val, 4, 2); 2695 2696 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2697 return MCDisassembler::Fail; 2698 if (!align) 2699 Inst.addOperand(MCOperand::createImm(0)); 2700 else 2701 Inst.addOperand(MCOperand::createImm(4 << align)); 2702 2703 return S; 2704 } 2705 2706 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2707 uint64_t Address, const void *Decoder) { 2708 DecodeStatus S = MCDisassembler::Success; 2709 2710 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2711 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2712 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2713 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2714 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2715 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2716 2717 // First output register 2718 switch (Inst.getOpcode()) { 2719 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2720 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2721 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2722 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2723 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2724 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2725 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2726 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2727 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2728 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2729 return MCDisassembler::Fail; 2730 break; 2731 case ARM::VLD2b16: 2732 case ARM::VLD2b32: 2733 case ARM::VLD2b8: 2734 case ARM::VLD2b16wb_fixed: 2735 case ARM::VLD2b16wb_register: 2736 case ARM::VLD2b32wb_fixed: 2737 case ARM::VLD2b32wb_register: 2738 case ARM::VLD2b8wb_fixed: 2739 case ARM::VLD2b8wb_register: 2740 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2741 return MCDisassembler::Fail; 2742 break; 2743 default: 2744 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2745 return MCDisassembler::Fail; 2746 } 2747 2748 // Second output register 2749 switch (Inst.getOpcode()) { 2750 case ARM::VLD3d8: 2751 case ARM::VLD3d16: 2752 case ARM::VLD3d32: 2753 case ARM::VLD3d8_UPD: 2754 case ARM::VLD3d16_UPD: 2755 case ARM::VLD3d32_UPD: 2756 case ARM::VLD4d8: 2757 case ARM::VLD4d16: 2758 case ARM::VLD4d32: 2759 case ARM::VLD4d8_UPD: 2760 case ARM::VLD4d16_UPD: 2761 case ARM::VLD4d32_UPD: 2762 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2763 return MCDisassembler::Fail; 2764 break; 2765 case ARM::VLD3q8: 2766 case ARM::VLD3q16: 2767 case ARM::VLD3q32: 2768 case ARM::VLD3q8_UPD: 2769 case ARM::VLD3q16_UPD: 2770 case ARM::VLD3q32_UPD: 2771 case ARM::VLD4q8: 2772 case ARM::VLD4q16: 2773 case ARM::VLD4q32: 2774 case ARM::VLD4q8_UPD: 2775 case ARM::VLD4q16_UPD: 2776 case ARM::VLD4q32_UPD: 2777 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2778 return MCDisassembler::Fail; 2779 break; 2780 default: 2781 break; 2782 } 2783 2784 // Third output register 2785 switch(Inst.getOpcode()) { 2786 case ARM::VLD3d8: 2787 case ARM::VLD3d16: 2788 case ARM::VLD3d32: 2789 case ARM::VLD3d8_UPD: 2790 case ARM::VLD3d16_UPD: 2791 case ARM::VLD3d32_UPD: 2792 case ARM::VLD4d8: 2793 case ARM::VLD4d16: 2794 case ARM::VLD4d32: 2795 case ARM::VLD4d8_UPD: 2796 case ARM::VLD4d16_UPD: 2797 case ARM::VLD4d32_UPD: 2798 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2799 return MCDisassembler::Fail; 2800 break; 2801 case ARM::VLD3q8: 2802 case ARM::VLD3q16: 2803 case ARM::VLD3q32: 2804 case ARM::VLD3q8_UPD: 2805 case ARM::VLD3q16_UPD: 2806 case ARM::VLD3q32_UPD: 2807 case ARM::VLD4q8: 2808 case ARM::VLD4q16: 2809 case ARM::VLD4q32: 2810 case ARM::VLD4q8_UPD: 2811 case ARM::VLD4q16_UPD: 2812 case ARM::VLD4q32_UPD: 2813 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2814 return MCDisassembler::Fail; 2815 break; 2816 default: 2817 break; 2818 } 2819 2820 // Fourth output register 2821 switch (Inst.getOpcode()) { 2822 case ARM::VLD4d8: 2823 case ARM::VLD4d16: 2824 case ARM::VLD4d32: 2825 case ARM::VLD4d8_UPD: 2826 case ARM::VLD4d16_UPD: 2827 case ARM::VLD4d32_UPD: 2828 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2829 return MCDisassembler::Fail; 2830 break; 2831 case ARM::VLD4q8: 2832 case ARM::VLD4q16: 2833 case ARM::VLD4q32: 2834 case ARM::VLD4q8_UPD: 2835 case ARM::VLD4q16_UPD: 2836 case ARM::VLD4q32_UPD: 2837 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2838 return MCDisassembler::Fail; 2839 break; 2840 default: 2841 break; 2842 } 2843 2844 // Writeback operand 2845 switch (Inst.getOpcode()) { 2846 case ARM::VLD1d8wb_fixed: 2847 case ARM::VLD1d16wb_fixed: 2848 case ARM::VLD1d32wb_fixed: 2849 case ARM::VLD1d64wb_fixed: 2850 case ARM::VLD1d8wb_register: 2851 case ARM::VLD1d16wb_register: 2852 case ARM::VLD1d32wb_register: 2853 case ARM::VLD1d64wb_register: 2854 case ARM::VLD1q8wb_fixed: 2855 case ARM::VLD1q16wb_fixed: 2856 case ARM::VLD1q32wb_fixed: 2857 case ARM::VLD1q64wb_fixed: 2858 case ARM::VLD1q8wb_register: 2859 case ARM::VLD1q16wb_register: 2860 case ARM::VLD1q32wb_register: 2861 case ARM::VLD1q64wb_register: 2862 case ARM::VLD1d8Twb_fixed: 2863 case ARM::VLD1d8Twb_register: 2864 case ARM::VLD1d16Twb_fixed: 2865 case ARM::VLD1d16Twb_register: 2866 case ARM::VLD1d32Twb_fixed: 2867 case ARM::VLD1d32Twb_register: 2868 case ARM::VLD1d64Twb_fixed: 2869 case ARM::VLD1d64Twb_register: 2870 case ARM::VLD1d8Qwb_fixed: 2871 case ARM::VLD1d8Qwb_register: 2872 case ARM::VLD1d16Qwb_fixed: 2873 case ARM::VLD1d16Qwb_register: 2874 case ARM::VLD1d32Qwb_fixed: 2875 case ARM::VLD1d32Qwb_register: 2876 case ARM::VLD1d64Qwb_fixed: 2877 case ARM::VLD1d64Qwb_register: 2878 case ARM::VLD2d8wb_fixed: 2879 case ARM::VLD2d16wb_fixed: 2880 case ARM::VLD2d32wb_fixed: 2881 case ARM::VLD2q8wb_fixed: 2882 case ARM::VLD2q16wb_fixed: 2883 case ARM::VLD2q32wb_fixed: 2884 case ARM::VLD2d8wb_register: 2885 case ARM::VLD2d16wb_register: 2886 case ARM::VLD2d32wb_register: 2887 case ARM::VLD2q8wb_register: 2888 case ARM::VLD2q16wb_register: 2889 case ARM::VLD2q32wb_register: 2890 case ARM::VLD2b8wb_fixed: 2891 case ARM::VLD2b16wb_fixed: 2892 case ARM::VLD2b32wb_fixed: 2893 case ARM::VLD2b8wb_register: 2894 case ARM::VLD2b16wb_register: 2895 case ARM::VLD2b32wb_register: 2896 Inst.addOperand(MCOperand::createImm(0)); 2897 break; 2898 case ARM::VLD3d8_UPD: 2899 case ARM::VLD3d16_UPD: 2900 case ARM::VLD3d32_UPD: 2901 case ARM::VLD3q8_UPD: 2902 case ARM::VLD3q16_UPD: 2903 case ARM::VLD3q32_UPD: 2904 case ARM::VLD4d8_UPD: 2905 case ARM::VLD4d16_UPD: 2906 case ARM::VLD4d32_UPD: 2907 case ARM::VLD4q8_UPD: 2908 case ARM::VLD4q16_UPD: 2909 case ARM::VLD4q32_UPD: 2910 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2911 return MCDisassembler::Fail; 2912 break; 2913 default: 2914 break; 2915 } 2916 2917 // AddrMode6 Base (register+alignment) 2918 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2919 return MCDisassembler::Fail; 2920 2921 // AddrMode6 Offset (register) 2922 switch (Inst.getOpcode()) { 2923 default: 2924 // The below have been updated to have explicit am6offset split 2925 // between fixed and register offset. For those instructions not 2926 // yet updated, we need to add an additional reg0 operand for the 2927 // fixed variant. 2928 // 2929 // The fixed offset encodes as Rm == 0xd, so we check for that. 2930 if (Rm == 0xd) { 2931 Inst.addOperand(MCOperand::createReg(0)); 2932 break; 2933 } 2934 // Fall through to handle the register offset variant. 2935 LLVM_FALLTHROUGH; 2936 case ARM::VLD1d8wb_fixed: 2937 case ARM::VLD1d16wb_fixed: 2938 case ARM::VLD1d32wb_fixed: 2939 case ARM::VLD1d64wb_fixed: 2940 case ARM::VLD1d8Twb_fixed: 2941 case ARM::VLD1d16Twb_fixed: 2942 case ARM::VLD1d32Twb_fixed: 2943 case ARM::VLD1d64Twb_fixed: 2944 case ARM::VLD1d8Qwb_fixed: 2945 case ARM::VLD1d16Qwb_fixed: 2946 case ARM::VLD1d32Qwb_fixed: 2947 case ARM::VLD1d64Qwb_fixed: 2948 case ARM::VLD1d8wb_register: 2949 case ARM::VLD1d16wb_register: 2950 case ARM::VLD1d32wb_register: 2951 case ARM::VLD1d64wb_register: 2952 case ARM::VLD1q8wb_fixed: 2953 case ARM::VLD1q16wb_fixed: 2954 case ARM::VLD1q32wb_fixed: 2955 case ARM::VLD1q64wb_fixed: 2956 case ARM::VLD1q8wb_register: 2957 case ARM::VLD1q16wb_register: 2958 case ARM::VLD1q32wb_register: 2959 case ARM::VLD1q64wb_register: 2960 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2961 // variant encodes Rm == 0xf. Anything else is a register offset post- 2962 // increment and we need to add the register operand to the instruction. 2963 if (Rm != 0xD && Rm != 0xF && 2964 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2965 return MCDisassembler::Fail; 2966 break; 2967 case ARM::VLD2d8wb_fixed: 2968 case ARM::VLD2d16wb_fixed: 2969 case ARM::VLD2d32wb_fixed: 2970 case ARM::VLD2b8wb_fixed: 2971 case ARM::VLD2b16wb_fixed: 2972 case ARM::VLD2b32wb_fixed: 2973 case ARM::VLD2q8wb_fixed: 2974 case ARM::VLD2q16wb_fixed: 2975 case ARM::VLD2q32wb_fixed: 2976 break; 2977 } 2978 2979 return S; 2980 } 2981 2982 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2983 uint64_t Address, const void *Decoder) { 2984 unsigned type = fieldFromInstruction(Insn, 8, 4); 2985 unsigned align = fieldFromInstruction(Insn, 4, 2); 2986 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2987 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2988 if (type == 10 && align == 3) return MCDisassembler::Fail; 2989 2990 unsigned load = fieldFromInstruction(Insn, 21, 1); 2991 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2992 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2993 } 2994 2995 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2996 uint64_t Address, const void *Decoder) { 2997 unsigned size = fieldFromInstruction(Insn, 6, 2); 2998 if (size == 3) return MCDisassembler::Fail; 2999 3000 unsigned type = fieldFromInstruction(Insn, 8, 4); 3001 unsigned align = fieldFromInstruction(Insn, 4, 2); 3002 if (type == 8 && align == 3) return MCDisassembler::Fail; 3003 if (type == 9 && align == 3) return MCDisassembler::Fail; 3004 3005 unsigned load = fieldFromInstruction(Insn, 21, 1); 3006 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3007 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3008 } 3009 3010 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 3011 uint64_t Address, const void *Decoder) { 3012 unsigned size = fieldFromInstruction(Insn, 6, 2); 3013 if (size == 3) return MCDisassembler::Fail; 3014 3015 unsigned align = fieldFromInstruction(Insn, 4, 2); 3016 if (align & 2) return MCDisassembler::Fail; 3017 3018 unsigned load = fieldFromInstruction(Insn, 21, 1); 3019 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3020 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3021 } 3022 3023 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 3024 uint64_t Address, const void *Decoder) { 3025 unsigned size = fieldFromInstruction(Insn, 6, 2); 3026 if (size == 3) return MCDisassembler::Fail; 3027 3028 unsigned load = fieldFromInstruction(Insn, 21, 1); 3029 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3030 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3031 } 3032 3033 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 3034 uint64_t Address, const void *Decoder) { 3035 DecodeStatus S = MCDisassembler::Success; 3036 3037 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3038 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3039 unsigned wb = fieldFromInstruction(Insn, 16, 4); 3040 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3041 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 3042 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3043 3044 // Writeback Operand 3045 switch (Inst.getOpcode()) { 3046 case ARM::VST1d8wb_fixed: 3047 case ARM::VST1d16wb_fixed: 3048 case ARM::VST1d32wb_fixed: 3049 case ARM::VST1d64wb_fixed: 3050 case ARM::VST1d8wb_register: 3051 case ARM::VST1d16wb_register: 3052 case ARM::VST1d32wb_register: 3053 case ARM::VST1d64wb_register: 3054 case ARM::VST1q8wb_fixed: 3055 case ARM::VST1q16wb_fixed: 3056 case ARM::VST1q32wb_fixed: 3057 case ARM::VST1q64wb_fixed: 3058 case ARM::VST1q8wb_register: 3059 case ARM::VST1q16wb_register: 3060 case ARM::VST1q32wb_register: 3061 case ARM::VST1q64wb_register: 3062 case ARM::VST1d8Twb_fixed: 3063 case ARM::VST1d16Twb_fixed: 3064 case ARM::VST1d32Twb_fixed: 3065 case ARM::VST1d64Twb_fixed: 3066 case ARM::VST1d8Twb_register: 3067 case ARM::VST1d16Twb_register: 3068 case ARM::VST1d32Twb_register: 3069 case ARM::VST1d64Twb_register: 3070 case ARM::VST1d8Qwb_fixed: 3071 case ARM::VST1d16Qwb_fixed: 3072 case ARM::VST1d32Qwb_fixed: 3073 case ARM::VST1d64Qwb_fixed: 3074 case ARM::VST1d8Qwb_register: 3075 case ARM::VST1d16Qwb_register: 3076 case ARM::VST1d32Qwb_register: 3077 case ARM::VST1d64Qwb_register: 3078 case ARM::VST2d8wb_fixed: 3079 case ARM::VST2d16wb_fixed: 3080 case ARM::VST2d32wb_fixed: 3081 case ARM::VST2d8wb_register: 3082 case ARM::VST2d16wb_register: 3083 case ARM::VST2d32wb_register: 3084 case ARM::VST2q8wb_fixed: 3085 case ARM::VST2q16wb_fixed: 3086 case ARM::VST2q32wb_fixed: 3087 case ARM::VST2q8wb_register: 3088 case ARM::VST2q16wb_register: 3089 case ARM::VST2q32wb_register: 3090 case ARM::VST2b8wb_fixed: 3091 case ARM::VST2b16wb_fixed: 3092 case ARM::VST2b32wb_fixed: 3093 case ARM::VST2b8wb_register: 3094 case ARM::VST2b16wb_register: 3095 case ARM::VST2b32wb_register: 3096 if (Rm == 0xF) 3097 return MCDisassembler::Fail; 3098 Inst.addOperand(MCOperand::createImm(0)); 3099 break; 3100 case ARM::VST3d8_UPD: 3101 case ARM::VST3d16_UPD: 3102 case ARM::VST3d32_UPD: 3103 case ARM::VST3q8_UPD: 3104 case ARM::VST3q16_UPD: 3105 case ARM::VST3q32_UPD: 3106 case ARM::VST4d8_UPD: 3107 case ARM::VST4d16_UPD: 3108 case ARM::VST4d32_UPD: 3109 case ARM::VST4q8_UPD: 3110 case ARM::VST4q16_UPD: 3111 case ARM::VST4q32_UPD: 3112 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3113 return MCDisassembler::Fail; 3114 break; 3115 default: 3116 break; 3117 } 3118 3119 // AddrMode6 Base (register+alignment) 3120 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3121 return MCDisassembler::Fail; 3122 3123 // AddrMode6 Offset (register) 3124 switch (Inst.getOpcode()) { 3125 default: 3126 if (Rm == 0xD) 3127 Inst.addOperand(MCOperand::createReg(0)); 3128 else if (Rm != 0xF) { 3129 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3130 return MCDisassembler::Fail; 3131 } 3132 break; 3133 case ARM::VST1d8wb_fixed: 3134 case ARM::VST1d16wb_fixed: 3135 case ARM::VST1d32wb_fixed: 3136 case ARM::VST1d64wb_fixed: 3137 case ARM::VST1q8wb_fixed: 3138 case ARM::VST1q16wb_fixed: 3139 case ARM::VST1q32wb_fixed: 3140 case ARM::VST1q64wb_fixed: 3141 case ARM::VST1d8Twb_fixed: 3142 case ARM::VST1d16Twb_fixed: 3143 case ARM::VST1d32Twb_fixed: 3144 case ARM::VST1d64Twb_fixed: 3145 case ARM::VST1d8Qwb_fixed: 3146 case ARM::VST1d16Qwb_fixed: 3147 case ARM::VST1d32Qwb_fixed: 3148 case ARM::VST1d64Qwb_fixed: 3149 case ARM::VST2d8wb_fixed: 3150 case ARM::VST2d16wb_fixed: 3151 case ARM::VST2d32wb_fixed: 3152 case ARM::VST2q8wb_fixed: 3153 case ARM::VST2q16wb_fixed: 3154 case ARM::VST2q32wb_fixed: 3155 case ARM::VST2b8wb_fixed: 3156 case ARM::VST2b16wb_fixed: 3157 case ARM::VST2b32wb_fixed: 3158 break; 3159 } 3160 3161 // First input register 3162 switch (Inst.getOpcode()) { 3163 case ARM::VST1q16: 3164 case ARM::VST1q32: 3165 case ARM::VST1q64: 3166 case ARM::VST1q8: 3167 case ARM::VST1q16wb_fixed: 3168 case ARM::VST1q16wb_register: 3169 case ARM::VST1q32wb_fixed: 3170 case ARM::VST1q32wb_register: 3171 case ARM::VST1q64wb_fixed: 3172 case ARM::VST1q64wb_register: 3173 case ARM::VST1q8wb_fixed: 3174 case ARM::VST1q8wb_register: 3175 case ARM::VST2d16: 3176 case ARM::VST2d32: 3177 case ARM::VST2d8: 3178 case ARM::VST2d16wb_fixed: 3179 case ARM::VST2d16wb_register: 3180 case ARM::VST2d32wb_fixed: 3181 case ARM::VST2d32wb_register: 3182 case ARM::VST2d8wb_fixed: 3183 case ARM::VST2d8wb_register: 3184 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3185 return MCDisassembler::Fail; 3186 break; 3187 case ARM::VST2b16: 3188 case ARM::VST2b32: 3189 case ARM::VST2b8: 3190 case ARM::VST2b16wb_fixed: 3191 case ARM::VST2b16wb_register: 3192 case ARM::VST2b32wb_fixed: 3193 case ARM::VST2b32wb_register: 3194 case ARM::VST2b8wb_fixed: 3195 case ARM::VST2b8wb_register: 3196 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3197 return MCDisassembler::Fail; 3198 break; 3199 default: 3200 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3201 return MCDisassembler::Fail; 3202 } 3203 3204 // Second input register 3205 switch (Inst.getOpcode()) { 3206 case ARM::VST3d8: 3207 case ARM::VST3d16: 3208 case ARM::VST3d32: 3209 case ARM::VST3d8_UPD: 3210 case ARM::VST3d16_UPD: 3211 case ARM::VST3d32_UPD: 3212 case ARM::VST4d8: 3213 case ARM::VST4d16: 3214 case ARM::VST4d32: 3215 case ARM::VST4d8_UPD: 3216 case ARM::VST4d16_UPD: 3217 case ARM::VST4d32_UPD: 3218 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3219 return MCDisassembler::Fail; 3220 break; 3221 case ARM::VST3q8: 3222 case ARM::VST3q16: 3223 case ARM::VST3q32: 3224 case ARM::VST3q8_UPD: 3225 case ARM::VST3q16_UPD: 3226 case ARM::VST3q32_UPD: 3227 case ARM::VST4q8: 3228 case ARM::VST4q16: 3229 case ARM::VST4q32: 3230 case ARM::VST4q8_UPD: 3231 case ARM::VST4q16_UPD: 3232 case ARM::VST4q32_UPD: 3233 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3234 return MCDisassembler::Fail; 3235 break; 3236 default: 3237 break; 3238 } 3239 3240 // Third input register 3241 switch (Inst.getOpcode()) { 3242 case ARM::VST3d8: 3243 case ARM::VST3d16: 3244 case ARM::VST3d32: 3245 case ARM::VST3d8_UPD: 3246 case ARM::VST3d16_UPD: 3247 case ARM::VST3d32_UPD: 3248 case ARM::VST4d8: 3249 case ARM::VST4d16: 3250 case ARM::VST4d32: 3251 case ARM::VST4d8_UPD: 3252 case ARM::VST4d16_UPD: 3253 case ARM::VST4d32_UPD: 3254 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3255 return MCDisassembler::Fail; 3256 break; 3257 case ARM::VST3q8: 3258 case ARM::VST3q16: 3259 case ARM::VST3q32: 3260 case ARM::VST3q8_UPD: 3261 case ARM::VST3q16_UPD: 3262 case ARM::VST3q32_UPD: 3263 case ARM::VST4q8: 3264 case ARM::VST4q16: 3265 case ARM::VST4q32: 3266 case ARM::VST4q8_UPD: 3267 case ARM::VST4q16_UPD: 3268 case ARM::VST4q32_UPD: 3269 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3270 return MCDisassembler::Fail; 3271 break; 3272 default: 3273 break; 3274 } 3275 3276 // Fourth input register 3277 switch (Inst.getOpcode()) { 3278 case ARM::VST4d8: 3279 case ARM::VST4d16: 3280 case ARM::VST4d32: 3281 case ARM::VST4d8_UPD: 3282 case ARM::VST4d16_UPD: 3283 case ARM::VST4d32_UPD: 3284 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3285 return MCDisassembler::Fail; 3286 break; 3287 case ARM::VST4q8: 3288 case ARM::VST4q16: 3289 case ARM::VST4q32: 3290 case ARM::VST4q8_UPD: 3291 case ARM::VST4q16_UPD: 3292 case ARM::VST4q32_UPD: 3293 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3294 return MCDisassembler::Fail; 3295 break; 3296 default: 3297 break; 3298 } 3299 3300 return S; 3301 } 3302 3303 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3304 uint64_t Address, const void *Decoder) { 3305 DecodeStatus S = MCDisassembler::Success; 3306 3307 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3308 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3309 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3310 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3311 unsigned align = fieldFromInstruction(Insn, 4, 1); 3312 unsigned size = fieldFromInstruction(Insn, 6, 2); 3313 3314 if (size == 0 && align == 1) 3315 return MCDisassembler::Fail; 3316 align *= (1 << size); 3317 3318 switch (Inst.getOpcode()) { 3319 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3320 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3321 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3322 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3323 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3324 return MCDisassembler::Fail; 3325 break; 3326 default: 3327 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3328 return MCDisassembler::Fail; 3329 break; 3330 } 3331 if (Rm != 0xF) { 3332 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3333 return MCDisassembler::Fail; 3334 } 3335 3336 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3337 return MCDisassembler::Fail; 3338 Inst.addOperand(MCOperand::createImm(align)); 3339 3340 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3341 // variant encodes Rm == 0xf. Anything else is a register offset post- 3342 // increment and we need to add the register operand to the instruction. 3343 if (Rm != 0xD && Rm != 0xF && 3344 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3345 return MCDisassembler::Fail; 3346 3347 return S; 3348 } 3349 3350 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3351 uint64_t Address, const void *Decoder) { 3352 DecodeStatus S = MCDisassembler::Success; 3353 3354 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3355 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3356 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3357 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3358 unsigned align = fieldFromInstruction(Insn, 4, 1); 3359 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3360 align *= 2*size; 3361 3362 switch (Inst.getOpcode()) { 3363 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3364 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3365 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3366 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3367 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3368 return MCDisassembler::Fail; 3369 break; 3370 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3371 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3372 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3373 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3374 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3375 return MCDisassembler::Fail; 3376 break; 3377 default: 3378 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3379 return MCDisassembler::Fail; 3380 break; 3381 } 3382 3383 if (Rm != 0xF) 3384 Inst.addOperand(MCOperand::createImm(0)); 3385 3386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3387 return MCDisassembler::Fail; 3388 Inst.addOperand(MCOperand::createImm(align)); 3389 3390 if (Rm != 0xD && Rm != 0xF) { 3391 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3392 return MCDisassembler::Fail; 3393 } 3394 3395 return S; 3396 } 3397 3398 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3399 uint64_t Address, const void *Decoder) { 3400 DecodeStatus S = MCDisassembler::Success; 3401 3402 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3403 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3404 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3405 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3406 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3407 3408 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3409 return MCDisassembler::Fail; 3410 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3411 return MCDisassembler::Fail; 3412 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3413 return MCDisassembler::Fail; 3414 if (Rm != 0xF) { 3415 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3416 return MCDisassembler::Fail; 3417 } 3418 3419 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3420 return MCDisassembler::Fail; 3421 Inst.addOperand(MCOperand::createImm(0)); 3422 3423 if (Rm == 0xD) 3424 Inst.addOperand(MCOperand::createReg(0)); 3425 else if (Rm != 0xF) { 3426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3427 return MCDisassembler::Fail; 3428 } 3429 3430 return S; 3431 } 3432 3433 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3434 uint64_t Address, const void *Decoder) { 3435 DecodeStatus S = MCDisassembler::Success; 3436 3437 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3438 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3439 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3440 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3441 unsigned size = fieldFromInstruction(Insn, 6, 2); 3442 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3443 unsigned align = fieldFromInstruction(Insn, 4, 1); 3444 3445 if (size == 0x3) { 3446 if (align == 0) 3447 return MCDisassembler::Fail; 3448 align = 16; 3449 } else { 3450 if (size == 2) { 3451 align *= 8; 3452 } else { 3453 size = 1 << size; 3454 align *= 4*size; 3455 } 3456 } 3457 3458 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3459 return MCDisassembler::Fail; 3460 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3461 return MCDisassembler::Fail; 3462 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3463 return MCDisassembler::Fail; 3464 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3465 return MCDisassembler::Fail; 3466 if (Rm != 0xF) { 3467 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3468 return MCDisassembler::Fail; 3469 } 3470 3471 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3472 return MCDisassembler::Fail; 3473 Inst.addOperand(MCOperand::createImm(align)); 3474 3475 if (Rm == 0xD) 3476 Inst.addOperand(MCOperand::createReg(0)); 3477 else if (Rm != 0xF) { 3478 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3479 return MCDisassembler::Fail; 3480 } 3481 3482 return S; 3483 } 3484 3485 static DecodeStatus 3486 DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, 3487 uint64_t Address, const void *Decoder) { 3488 DecodeStatus S = MCDisassembler::Success; 3489 3490 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3491 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3492 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3493 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3494 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3495 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3496 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3497 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3498 3499 if (Q) { 3500 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3501 return MCDisassembler::Fail; 3502 } else { 3503 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3504 return MCDisassembler::Fail; 3505 } 3506 3507 Inst.addOperand(MCOperand::createImm(imm)); 3508 3509 switch (Inst.getOpcode()) { 3510 case ARM::VORRiv4i16: 3511 case ARM::VORRiv2i32: 3512 case ARM::VBICiv4i16: 3513 case ARM::VBICiv2i32: 3514 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3515 return MCDisassembler::Fail; 3516 break; 3517 case ARM::VORRiv8i16: 3518 case ARM::VORRiv4i32: 3519 case ARM::VBICiv8i16: 3520 case ARM::VBICiv4i32: 3521 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3522 return MCDisassembler::Fail; 3523 break; 3524 default: 3525 break; 3526 } 3527 3528 return S; 3529 } 3530 3531 static DecodeStatus 3532 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3533 uint64_t Address, const void *Decoder) { 3534 DecodeStatus S = MCDisassembler::Success; 3535 3536 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3537 fieldFromInstruction(Insn, 13, 3)); 3538 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3539 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3540 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3541 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3542 imm |= cmode << 8; 3543 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3544 3545 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3546 return MCDisassembler::Fail; 3547 3548 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3549 return MCDisassembler::Fail; 3550 3551 Inst.addOperand(MCOperand::createImm(imm)); 3552 3553 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3554 Inst.addOperand(MCOperand::createReg(0)); 3555 Inst.addOperand(MCOperand::createImm(0)); 3556 3557 return S; 3558 } 3559 3560 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3561 uint64_t Address, const void *Decoder) { 3562 DecodeStatus S = MCDisassembler::Success; 3563 3564 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3565 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3566 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3567 return MCDisassembler::Fail; 3568 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3569 3570 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3571 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3572 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3573 return MCDisassembler::Fail; 3574 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3575 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3576 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3577 return MCDisassembler::Fail; 3578 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3579 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3580 Inst.addOperand(MCOperand::createImm(Qd)); 3581 3582 return S; 3583 } 3584 3585 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3586 uint64_t Address, const void *Decoder) { 3587 DecodeStatus S = MCDisassembler::Success; 3588 3589 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3590 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3591 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3592 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3593 unsigned size = fieldFromInstruction(Insn, 18, 2); 3594 3595 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3596 return MCDisassembler::Fail; 3597 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3598 return MCDisassembler::Fail; 3599 Inst.addOperand(MCOperand::createImm(8 << size)); 3600 3601 return S; 3602 } 3603 3604 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3605 uint64_t Address, const void *Decoder) { 3606 Inst.addOperand(MCOperand::createImm(8 - Val)); 3607 return MCDisassembler::Success; 3608 } 3609 3610 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3611 uint64_t Address, const void *Decoder) { 3612 Inst.addOperand(MCOperand::createImm(16 - Val)); 3613 return MCDisassembler::Success; 3614 } 3615 3616 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3617 uint64_t Address, const void *Decoder) { 3618 Inst.addOperand(MCOperand::createImm(32 - Val)); 3619 return MCDisassembler::Success; 3620 } 3621 3622 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3623 uint64_t Address, const void *Decoder) { 3624 Inst.addOperand(MCOperand::createImm(64 - Val)); 3625 return MCDisassembler::Success; 3626 } 3627 3628 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3629 uint64_t Address, const void *Decoder) { 3630 DecodeStatus S = MCDisassembler::Success; 3631 3632 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3633 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3634 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3635 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3636 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3637 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3638 unsigned op = fieldFromInstruction(Insn, 6, 1); 3639 3640 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3641 return MCDisassembler::Fail; 3642 if (op) { 3643 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3644 return MCDisassembler::Fail; // Writeback 3645 } 3646 3647 switch (Inst.getOpcode()) { 3648 case ARM::VTBL2: 3649 case ARM::VTBX2: 3650 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3651 return MCDisassembler::Fail; 3652 break; 3653 default: 3654 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3655 return MCDisassembler::Fail; 3656 } 3657 3658 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3659 return MCDisassembler::Fail; 3660 3661 return S; 3662 } 3663 3664 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3665 uint64_t Address, const void *Decoder) { 3666 DecodeStatus S = MCDisassembler::Success; 3667 3668 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3669 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3670 3671 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3672 return MCDisassembler::Fail; 3673 3674 switch(Inst.getOpcode()) { 3675 default: 3676 return MCDisassembler::Fail; 3677 case ARM::tADR: 3678 break; // tADR does not explicitly represent the PC as an operand. 3679 case ARM::tADDrSPi: 3680 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3681 break; 3682 } 3683 3684 Inst.addOperand(MCOperand::createImm(imm)); 3685 return S; 3686 } 3687 3688 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3689 uint64_t Address, const void *Decoder) { 3690 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3691 true, 2, Inst, Decoder)) 3692 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3693 return MCDisassembler::Success; 3694 } 3695 3696 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3697 uint64_t Address, const void *Decoder) { 3698 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3699 true, 4, Inst, Decoder)) 3700 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3701 return MCDisassembler::Success; 3702 } 3703 3704 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3705 uint64_t Address, const void *Decoder) { 3706 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3707 true, 2, Inst, Decoder)) 3708 Inst.addOperand(MCOperand::createImm(Val << 1)); 3709 return MCDisassembler::Success; 3710 } 3711 3712 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3713 uint64_t Address, const void *Decoder) { 3714 DecodeStatus S = MCDisassembler::Success; 3715 3716 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3717 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3718 3719 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3720 return MCDisassembler::Fail; 3721 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3722 return MCDisassembler::Fail; 3723 3724 return S; 3725 } 3726 3727 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3728 uint64_t Address, const void *Decoder) { 3729 DecodeStatus S = MCDisassembler::Success; 3730 3731 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3732 unsigned imm = fieldFromInstruction(Val, 3, 5); 3733 3734 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3735 return MCDisassembler::Fail; 3736 Inst.addOperand(MCOperand::createImm(imm)); 3737 3738 return S; 3739 } 3740 3741 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3742 uint64_t Address, const void *Decoder) { 3743 unsigned imm = Val << 2; 3744 3745 Inst.addOperand(MCOperand::createImm(imm)); 3746 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3747 3748 return MCDisassembler::Success; 3749 } 3750 3751 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3752 uint64_t Address, const void *Decoder) { 3753 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3754 Inst.addOperand(MCOperand::createImm(Val)); 3755 3756 return MCDisassembler::Success; 3757 } 3758 3759 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3760 uint64_t Address, const void *Decoder) { 3761 DecodeStatus S = MCDisassembler::Success; 3762 3763 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3764 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3765 unsigned imm = fieldFromInstruction(Val, 0, 2); 3766 3767 // Thumb stores cannot use PC as dest register. 3768 switch (Inst.getOpcode()) { 3769 case ARM::t2STRHs: 3770 case ARM::t2STRBs: 3771 case ARM::t2STRs: 3772 if (Rn == 15) 3773 return MCDisassembler::Fail; 3774 break; 3775 default: 3776 break; 3777 } 3778 3779 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3780 return MCDisassembler::Fail; 3781 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3782 return MCDisassembler::Fail; 3783 Inst.addOperand(MCOperand::createImm(imm)); 3784 3785 return S; 3786 } 3787 3788 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3789 uint64_t Address, const void *Decoder) { 3790 DecodeStatus S = MCDisassembler::Success; 3791 3792 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3793 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3794 3795 const FeatureBitset &featureBits = 3796 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3797 3798 bool hasMP = featureBits[ARM::FeatureMP]; 3799 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3800 3801 if (Rn == 15) { 3802 switch (Inst.getOpcode()) { 3803 case ARM::t2LDRBs: 3804 Inst.setOpcode(ARM::t2LDRBpci); 3805 break; 3806 case ARM::t2LDRHs: 3807 Inst.setOpcode(ARM::t2LDRHpci); 3808 break; 3809 case ARM::t2LDRSHs: 3810 Inst.setOpcode(ARM::t2LDRSHpci); 3811 break; 3812 case ARM::t2LDRSBs: 3813 Inst.setOpcode(ARM::t2LDRSBpci); 3814 break; 3815 case ARM::t2LDRs: 3816 Inst.setOpcode(ARM::t2LDRpci); 3817 break; 3818 case ARM::t2PLDs: 3819 Inst.setOpcode(ARM::t2PLDpci); 3820 break; 3821 case ARM::t2PLIs: 3822 Inst.setOpcode(ARM::t2PLIpci); 3823 break; 3824 default: 3825 return MCDisassembler::Fail; 3826 } 3827 3828 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3829 } 3830 3831 if (Rt == 15) { 3832 switch (Inst.getOpcode()) { 3833 case ARM::t2LDRSHs: 3834 return MCDisassembler::Fail; 3835 case ARM::t2LDRHs: 3836 Inst.setOpcode(ARM::t2PLDWs); 3837 break; 3838 case ARM::t2LDRSBs: 3839 Inst.setOpcode(ARM::t2PLIs); 3840 break; 3841 default: 3842 break; 3843 } 3844 } 3845 3846 switch (Inst.getOpcode()) { 3847 case ARM::t2PLDs: 3848 break; 3849 case ARM::t2PLIs: 3850 if (!hasV7Ops) 3851 return MCDisassembler::Fail; 3852 break; 3853 case ARM::t2PLDWs: 3854 if (!hasV7Ops || !hasMP) 3855 return MCDisassembler::Fail; 3856 break; 3857 default: 3858 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3859 return MCDisassembler::Fail; 3860 } 3861 3862 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3863 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3864 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3865 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3866 return MCDisassembler::Fail; 3867 3868 return S; 3869 } 3870 3871 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3872 uint64_t Address, const void* Decoder) { 3873 DecodeStatus S = MCDisassembler::Success; 3874 3875 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3876 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3877 unsigned U = fieldFromInstruction(Insn, 9, 1); 3878 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3879 imm |= (U << 8); 3880 imm |= (Rn << 9); 3881 unsigned add = fieldFromInstruction(Insn, 9, 1); 3882 3883 const FeatureBitset &featureBits = 3884 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3885 3886 bool hasMP = featureBits[ARM::FeatureMP]; 3887 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3888 3889 if (Rn == 15) { 3890 switch (Inst.getOpcode()) { 3891 case ARM::t2LDRi8: 3892 Inst.setOpcode(ARM::t2LDRpci); 3893 break; 3894 case ARM::t2LDRBi8: 3895 Inst.setOpcode(ARM::t2LDRBpci); 3896 break; 3897 case ARM::t2LDRSBi8: 3898 Inst.setOpcode(ARM::t2LDRSBpci); 3899 break; 3900 case ARM::t2LDRHi8: 3901 Inst.setOpcode(ARM::t2LDRHpci); 3902 break; 3903 case ARM::t2LDRSHi8: 3904 Inst.setOpcode(ARM::t2LDRSHpci); 3905 break; 3906 case ARM::t2PLDi8: 3907 Inst.setOpcode(ARM::t2PLDpci); 3908 break; 3909 case ARM::t2PLIi8: 3910 Inst.setOpcode(ARM::t2PLIpci); 3911 break; 3912 default: 3913 return MCDisassembler::Fail; 3914 } 3915 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3916 } 3917 3918 if (Rt == 15) { 3919 switch (Inst.getOpcode()) { 3920 case ARM::t2LDRSHi8: 3921 return MCDisassembler::Fail; 3922 case ARM::t2LDRHi8: 3923 if (!add) 3924 Inst.setOpcode(ARM::t2PLDWi8); 3925 break; 3926 case ARM::t2LDRSBi8: 3927 Inst.setOpcode(ARM::t2PLIi8); 3928 break; 3929 default: 3930 break; 3931 } 3932 } 3933 3934 switch (Inst.getOpcode()) { 3935 case ARM::t2PLDi8: 3936 break; 3937 case ARM::t2PLIi8: 3938 if (!hasV7Ops) 3939 return MCDisassembler::Fail; 3940 break; 3941 case ARM::t2PLDWi8: 3942 if (!hasV7Ops || !hasMP) 3943 return MCDisassembler::Fail; 3944 break; 3945 default: 3946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3947 return MCDisassembler::Fail; 3948 } 3949 3950 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3951 return MCDisassembler::Fail; 3952 return S; 3953 } 3954 3955 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3956 uint64_t Address, const void* Decoder) { 3957 DecodeStatus S = MCDisassembler::Success; 3958 3959 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3960 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3961 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3962 imm |= (Rn << 13); 3963 3964 const FeatureBitset &featureBits = 3965 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3966 3967 bool hasMP = featureBits[ARM::FeatureMP]; 3968 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3969 3970 if (Rn == 15) { 3971 switch (Inst.getOpcode()) { 3972 case ARM::t2LDRi12: 3973 Inst.setOpcode(ARM::t2LDRpci); 3974 break; 3975 case ARM::t2LDRHi12: 3976 Inst.setOpcode(ARM::t2LDRHpci); 3977 break; 3978 case ARM::t2LDRSHi12: 3979 Inst.setOpcode(ARM::t2LDRSHpci); 3980 break; 3981 case ARM::t2LDRBi12: 3982 Inst.setOpcode(ARM::t2LDRBpci); 3983 break; 3984 case ARM::t2LDRSBi12: 3985 Inst.setOpcode(ARM::t2LDRSBpci); 3986 break; 3987 case ARM::t2PLDi12: 3988 Inst.setOpcode(ARM::t2PLDpci); 3989 break; 3990 case ARM::t2PLIi12: 3991 Inst.setOpcode(ARM::t2PLIpci); 3992 break; 3993 default: 3994 return MCDisassembler::Fail; 3995 } 3996 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3997 } 3998 3999 if (Rt == 15) { 4000 switch (Inst.getOpcode()) { 4001 case ARM::t2LDRSHi12: 4002 return MCDisassembler::Fail; 4003 case ARM::t2LDRHi12: 4004 Inst.setOpcode(ARM::t2PLDWi12); 4005 break; 4006 case ARM::t2LDRSBi12: 4007 Inst.setOpcode(ARM::t2PLIi12); 4008 break; 4009 default: 4010 break; 4011 } 4012 } 4013 4014 switch (Inst.getOpcode()) { 4015 case ARM::t2PLDi12: 4016 break; 4017 case ARM::t2PLIi12: 4018 if (!hasV7Ops) 4019 return MCDisassembler::Fail; 4020 break; 4021 case ARM::t2PLDWi12: 4022 if (!hasV7Ops || !hasMP) 4023 return MCDisassembler::Fail; 4024 break; 4025 default: 4026 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4027 return MCDisassembler::Fail; 4028 } 4029 4030 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 4031 return MCDisassembler::Fail; 4032 return S; 4033 } 4034 4035 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 4036 uint64_t Address, const void* Decoder) { 4037 DecodeStatus S = MCDisassembler::Success; 4038 4039 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4040 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4041 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4042 imm |= (Rn << 9); 4043 4044 if (Rn == 15) { 4045 switch (Inst.getOpcode()) { 4046 case ARM::t2LDRT: 4047 Inst.setOpcode(ARM::t2LDRpci); 4048 break; 4049 case ARM::t2LDRBT: 4050 Inst.setOpcode(ARM::t2LDRBpci); 4051 break; 4052 case ARM::t2LDRHT: 4053 Inst.setOpcode(ARM::t2LDRHpci); 4054 break; 4055 case ARM::t2LDRSBT: 4056 Inst.setOpcode(ARM::t2LDRSBpci); 4057 break; 4058 case ARM::t2LDRSHT: 4059 Inst.setOpcode(ARM::t2LDRSHpci); 4060 break; 4061 default: 4062 return MCDisassembler::Fail; 4063 } 4064 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4065 } 4066 4067 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4068 return MCDisassembler::Fail; 4069 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4070 return MCDisassembler::Fail; 4071 return S; 4072 } 4073 4074 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4075 uint64_t Address, const void* Decoder) { 4076 DecodeStatus S = MCDisassembler::Success; 4077 4078 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4079 unsigned U = fieldFromInstruction(Insn, 23, 1); 4080 int imm = fieldFromInstruction(Insn, 0, 12); 4081 4082 const FeatureBitset &featureBits = 4083 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4084 4085 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4086 4087 if (Rt == 15) { 4088 switch (Inst.getOpcode()) { 4089 case ARM::t2LDRBpci: 4090 case ARM::t2LDRHpci: 4091 Inst.setOpcode(ARM::t2PLDpci); 4092 break; 4093 case ARM::t2LDRSBpci: 4094 Inst.setOpcode(ARM::t2PLIpci); 4095 break; 4096 case ARM::t2LDRSHpci: 4097 return MCDisassembler::Fail; 4098 default: 4099 break; 4100 } 4101 } 4102 4103 switch(Inst.getOpcode()) { 4104 case ARM::t2PLDpci: 4105 break; 4106 case ARM::t2PLIpci: 4107 if (!hasV7Ops) 4108 return MCDisassembler::Fail; 4109 break; 4110 default: 4111 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4112 return MCDisassembler::Fail; 4113 } 4114 4115 if (!U) { 4116 // Special case for #-0. 4117 if (imm == 0) 4118 imm = INT32_MIN; 4119 else 4120 imm = -imm; 4121 } 4122 Inst.addOperand(MCOperand::createImm(imm)); 4123 4124 return S; 4125 } 4126 4127 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 4128 uint64_t Address, const void *Decoder) { 4129 if (Val == 0) 4130 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4131 else { 4132 int imm = Val & 0xFF; 4133 4134 if (!(Val & 0x100)) imm *= -1; 4135 Inst.addOperand(MCOperand::createImm(imm * 4)); 4136 } 4137 4138 return MCDisassembler::Success; 4139 } 4140 4141 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4142 const void *Decoder) { 4143 if (Val == 0) 4144 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4145 else { 4146 int imm = Val & 0x7F; 4147 4148 if (!(Val & 0x80)) 4149 imm *= -1; 4150 Inst.addOperand(MCOperand::createImm(imm * 4)); 4151 } 4152 4153 return MCDisassembler::Success; 4154 } 4155 4156 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4157 uint64_t Address, const void *Decoder) { 4158 DecodeStatus S = MCDisassembler::Success; 4159 4160 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4161 unsigned imm = fieldFromInstruction(Val, 0, 9); 4162 4163 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4164 return MCDisassembler::Fail; 4165 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4166 return MCDisassembler::Fail; 4167 4168 return S; 4169 } 4170 4171 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4172 uint64_t Address, 4173 const void *Decoder) { 4174 DecodeStatus S = MCDisassembler::Success; 4175 4176 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4177 unsigned imm = fieldFromInstruction(Val, 0, 8); 4178 4179 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4180 return MCDisassembler::Fail; 4181 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4182 return MCDisassembler::Fail; 4183 4184 return S; 4185 } 4186 4187 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4188 uint64_t Address, const void *Decoder) { 4189 DecodeStatus S = MCDisassembler::Success; 4190 4191 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4192 unsigned imm = fieldFromInstruction(Val, 0, 8); 4193 4194 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4195 return MCDisassembler::Fail; 4196 4197 Inst.addOperand(MCOperand::createImm(imm)); 4198 4199 return S; 4200 } 4201 4202 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4203 uint64_t Address, const void *Decoder) { 4204 int imm = Val & 0xFF; 4205 if (Val == 0) 4206 imm = INT32_MIN; 4207 else if (!(Val & 0x100)) 4208 imm *= -1; 4209 Inst.addOperand(MCOperand::createImm(imm)); 4210 4211 return MCDisassembler::Success; 4212 } 4213 4214 template<int shift> 4215 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 4216 uint64_t Address, const void *Decoder) { 4217 int imm = Val & 0x7F; 4218 if (Val == 0) 4219 imm = INT32_MIN; 4220 else if (!(Val & 0x80)) 4221 imm *= -1; 4222 if (imm != INT32_MIN) 4223 imm *= (1U << shift); 4224 Inst.addOperand(MCOperand::createImm(imm)); 4225 4226 return MCDisassembler::Success; 4227 } 4228 4229 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4230 uint64_t Address, const void *Decoder) { 4231 DecodeStatus S = MCDisassembler::Success; 4232 4233 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4234 unsigned imm = fieldFromInstruction(Val, 0, 9); 4235 4236 // Thumb stores cannot use PC as dest register. 4237 switch (Inst.getOpcode()) { 4238 case ARM::t2STRT: 4239 case ARM::t2STRBT: 4240 case ARM::t2STRHT: 4241 case ARM::t2STRi8: 4242 case ARM::t2STRHi8: 4243 case ARM::t2STRBi8: 4244 if (Rn == 15) 4245 return MCDisassembler::Fail; 4246 break; 4247 default: 4248 break; 4249 } 4250 4251 // Some instructions always use an additive offset. 4252 switch (Inst.getOpcode()) { 4253 case ARM::t2LDRT: 4254 case ARM::t2LDRBT: 4255 case ARM::t2LDRHT: 4256 case ARM::t2LDRSBT: 4257 case ARM::t2LDRSHT: 4258 case ARM::t2STRT: 4259 case ARM::t2STRBT: 4260 case ARM::t2STRHT: 4261 imm |= 0x100; 4262 break; 4263 default: 4264 break; 4265 } 4266 4267 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4268 return MCDisassembler::Fail; 4269 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4270 return MCDisassembler::Fail; 4271 4272 return S; 4273 } 4274 4275 template<int shift> 4276 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4277 uint64_t Address, 4278 const void *Decoder) { 4279 DecodeStatus S = MCDisassembler::Success; 4280 4281 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4282 unsigned imm = fieldFromInstruction(Val, 0, 8); 4283 4284 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4285 return MCDisassembler::Fail; 4286 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4287 return MCDisassembler::Fail; 4288 4289 return S; 4290 } 4291 4292 template<int shift, int WriteBack> 4293 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4294 uint64_t Address, 4295 const void *Decoder) { 4296 DecodeStatus S = MCDisassembler::Success; 4297 4298 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4299 unsigned imm = fieldFromInstruction(Val, 0, 8); 4300 if (WriteBack) { 4301 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4302 return MCDisassembler::Fail; 4303 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4304 return MCDisassembler::Fail; 4305 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4306 return MCDisassembler::Fail; 4307 4308 return S; 4309 } 4310 4311 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4312 uint64_t Address, const void *Decoder) { 4313 DecodeStatus S = MCDisassembler::Success; 4314 4315 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4316 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4317 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4318 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4319 addr |= Rn << 9; 4320 unsigned load = fieldFromInstruction(Insn, 20, 1); 4321 4322 if (Rn == 15) { 4323 switch (Inst.getOpcode()) { 4324 case ARM::t2LDR_PRE: 4325 case ARM::t2LDR_POST: 4326 Inst.setOpcode(ARM::t2LDRpci); 4327 break; 4328 case ARM::t2LDRB_PRE: 4329 case ARM::t2LDRB_POST: 4330 Inst.setOpcode(ARM::t2LDRBpci); 4331 break; 4332 case ARM::t2LDRH_PRE: 4333 case ARM::t2LDRH_POST: 4334 Inst.setOpcode(ARM::t2LDRHpci); 4335 break; 4336 case ARM::t2LDRSB_PRE: 4337 case ARM::t2LDRSB_POST: 4338 if (Rt == 15) 4339 Inst.setOpcode(ARM::t2PLIpci); 4340 else 4341 Inst.setOpcode(ARM::t2LDRSBpci); 4342 break; 4343 case ARM::t2LDRSH_PRE: 4344 case ARM::t2LDRSH_POST: 4345 Inst.setOpcode(ARM::t2LDRSHpci); 4346 break; 4347 default: 4348 return MCDisassembler::Fail; 4349 } 4350 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4351 } 4352 4353 if (!load) { 4354 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4355 return MCDisassembler::Fail; 4356 } 4357 4358 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4359 return MCDisassembler::Fail; 4360 4361 if (load) { 4362 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4363 return MCDisassembler::Fail; 4364 } 4365 4366 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4367 return MCDisassembler::Fail; 4368 4369 return S; 4370 } 4371 4372 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4373 uint64_t Address, const void *Decoder) { 4374 DecodeStatus S = MCDisassembler::Success; 4375 4376 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4377 unsigned imm = fieldFromInstruction(Val, 0, 12); 4378 4379 // Thumb stores cannot use PC as dest register. 4380 switch (Inst.getOpcode()) { 4381 case ARM::t2STRi12: 4382 case ARM::t2STRBi12: 4383 case ARM::t2STRHi12: 4384 if (Rn == 15) 4385 return MCDisassembler::Fail; 4386 break; 4387 default: 4388 break; 4389 } 4390 4391 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4392 return MCDisassembler::Fail; 4393 Inst.addOperand(MCOperand::createImm(imm)); 4394 4395 return S; 4396 } 4397 4398 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4399 uint64_t Address, const void *Decoder) { 4400 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4401 4402 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4403 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4404 Inst.addOperand(MCOperand::createImm(imm)); 4405 4406 return MCDisassembler::Success; 4407 } 4408 4409 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4410 uint64_t Address, const void *Decoder) { 4411 DecodeStatus S = MCDisassembler::Success; 4412 4413 if (Inst.getOpcode() == ARM::tADDrSP) { 4414 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4415 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4416 4417 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4418 return MCDisassembler::Fail; 4419 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4420 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4421 return MCDisassembler::Fail; 4422 } else if (Inst.getOpcode() == ARM::tADDspr) { 4423 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4424 4425 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4426 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4427 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4428 return MCDisassembler::Fail; 4429 } 4430 4431 return S; 4432 } 4433 4434 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4435 uint64_t Address, const void *Decoder) { 4436 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4437 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4438 4439 Inst.addOperand(MCOperand::createImm(imod)); 4440 Inst.addOperand(MCOperand::createImm(flags)); 4441 4442 return MCDisassembler::Success; 4443 } 4444 4445 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4446 uint64_t Address, const void *Decoder) { 4447 DecodeStatus S = MCDisassembler::Success; 4448 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4449 unsigned add = fieldFromInstruction(Insn, 4, 1); 4450 4451 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4452 return MCDisassembler::Fail; 4453 Inst.addOperand(MCOperand::createImm(add)); 4454 4455 return S; 4456 } 4457 4458 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4459 uint64_t Address, const void *Decoder) { 4460 DecodeStatus S = MCDisassembler::Success; 4461 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4462 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4463 4464 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4465 return MCDisassembler::Fail; 4466 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4467 return MCDisassembler::Fail; 4468 4469 return S; 4470 } 4471 4472 template<int shift> 4473 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4474 uint64_t Address, const void *Decoder) { 4475 DecodeStatus S = MCDisassembler::Success; 4476 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4477 int imm = fieldFromInstruction(Insn, 0, 7); 4478 4479 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4480 return MCDisassembler::Fail; 4481 4482 if(!fieldFromInstruction(Insn, 7, 1)) { 4483 if (imm == 0) 4484 imm = INT32_MIN; // indicate -0 4485 else 4486 imm *= -1; 4487 } 4488 if (imm != INT32_MIN) 4489 imm *= (1U << shift); 4490 Inst.addOperand(MCOperand::createImm(imm)); 4491 4492 return S; 4493 } 4494 4495 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4496 uint64_t Address, const void *Decoder) { 4497 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4498 // Note only one trailing zero not two. Also the J1 and J2 values are from 4499 // the encoded instruction. So here change to I1 and I2 values via: 4500 // I1 = NOT(J1 EOR S); 4501 // I2 = NOT(J2 EOR S); 4502 // and build the imm32 with two trailing zeros as documented: 4503 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4504 unsigned S = (Val >> 23) & 1; 4505 unsigned J1 = (Val >> 22) & 1; 4506 unsigned J2 = (Val >> 21) & 1; 4507 unsigned I1 = !(J1 ^ S); 4508 unsigned I2 = !(J2 ^ S); 4509 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4510 int imm32 = SignExtend32<25>(tmp << 1); 4511 4512 if (!tryAddingSymbolicOperand(Address, 4513 (Address & ~2u) + imm32 + 4, 4514 true, 4, Inst, Decoder)) 4515 Inst.addOperand(MCOperand::createImm(imm32)); 4516 return MCDisassembler::Success; 4517 } 4518 4519 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4520 uint64_t Address, const void *Decoder) { 4521 if (Val == 0xA || Val == 0xB) 4522 return MCDisassembler::Fail; 4523 4524 const FeatureBitset &featureBits = 4525 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4526 4527 if (!isValidCoprocessorNumber(Val, featureBits)) 4528 return MCDisassembler::Fail; 4529 4530 Inst.addOperand(MCOperand::createImm(Val)); 4531 return MCDisassembler::Success; 4532 } 4533 4534 static DecodeStatus 4535 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4536 uint64_t Address, const void *Decoder) { 4537 const FeatureBitset &FeatureBits = 4538 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4539 DecodeStatus S = MCDisassembler::Success; 4540 4541 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4542 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4543 4544 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; 4545 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4546 return MCDisassembler::Fail; 4547 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4548 return MCDisassembler::Fail; 4549 return S; 4550 } 4551 4552 static DecodeStatus 4553 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4554 uint64_t Address, const void *Decoder) { 4555 DecodeStatus S = MCDisassembler::Success; 4556 4557 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4558 if (pred == 0xE || pred == 0xF) { 4559 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4560 switch (opc) { 4561 default: 4562 return MCDisassembler::Fail; 4563 case 0xf3bf8f4: 4564 Inst.setOpcode(ARM::t2DSB); 4565 break; 4566 case 0xf3bf8f5: 4567 Inst.setOpcode(ARM::t2DMB); 4568 break; 4569 case 0xf3bf8f6: 4570 Inst.setOpcode(ARM::t2ISB); 4571 break; 4572 } 4573 4574 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4575 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4576 } 4577 4578 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4579 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4580 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4581 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4582 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4583 4584 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4585 return MCDisassembler::Fail; 4586 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4587 return MCDisassembler::Fail; 4588 4589 return S; 4590 } 4591 4592 // Decode a shifted immediate operand. These basically consist 4593 // of an 8-bit value, and a 4-bit directive that specifies either 4594 // a splat operation or a rotation. 4595 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4596 uint64_t Address, const void *Decoder) { 4597 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4598 if (ctrl == 0) { 4599 unsigned byte = fieldFromInstruction(Val, 8, 2); 4600 unsigned imm = fieldFromInstruction(Val, 0, 8); 4601 switch (byte) { 4602 case 0: 4603 Inst.addOperand(MCOperand::createImm(imm)); 4604 break; 4605 case 1: 4606 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4607 break; 4608 case 2: 4609 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4610 break; 4611 case 3: 4612 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4613 (imm << 8) | imm)); 4614 break; 4615 } 4616 } else { 4617 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4618 unsigned rot = fieldFromInstruction(Val, 7, 5); 4619 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4620 Inst.addOperand(MCOperand::createImm(imm)); 4621 } 4622 4623 return MCDisassembler::Success; 4624 } 4625 4626 static DecodeStatus 4627 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4628 uint64_t Address, const void *Decoder) { 4629 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4630 true, 2, Inst, Decoder)) 4631 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4632 return MCDisassembler::Success; 4633 } 4634 4635 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4636 uint64_t Address, 4637 const void *Decoder) { 4638 // Val is passed in as S:J1:J2:imm10:imm11 4639 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4640 // the encoded instruction. So here change to I1 and I2 values via: 4641 // I1 = NOT(J1 EOR S); 4642 // I2 = NOT(J2 EOR S); 4643 // and build the imm32 with one trailing zero as documented: 4644 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4645 unsigned S = (Val >> 23) & 1; 4646 unsigned J1 = (Val >> 22) & 1; 4647 unsigned J2 = (Val >> 21) & 1; 4648 unsigned I1 = !(J1 ^ S); 4649 unsigned I2 = !(J2 ^ S); 4650 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4651 int imm32 = SignExtend32<25>(tmp << 1); 4652 4653 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4654 true, 4, Inst, Decoder)) 4655 Inst.addOperand(MCOperand::createImm(imm32)); 4656 return MCDisassembler::Success; 4657 } 4658 4659 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4660 uint64_t Address, const void *Decoder) { 4661 if (Val & ~0xf) 4662 return MCDisassembler::Fail; 4663 4664 Inst.addOperand(MCOperand::createImm(Val)); 4665 return MCDisassembler::Success; 4666 } 4667 4668 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4669 uint64_t Address, const void *Decoder) { 4670 if (Val & ~0xf) 4671 return MCDisassembler::Fail; 4672 4673 Inst.addOperand(MCOperand::createImm(Val)); 4674 return MCDisassembler::Success; 4675 } 4676 4677 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4678 uint64_t Address, const void *Decoder) { 4679 DecodeStatus S = MCDisassembler::Success; 4680 const FeatureBitset &FeatureBits = 4681 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4682 4683 if (FeatureBits[ARM::FeatureMClass]) { 4684 unsigned ValLow = Val & 0xff; 4685 4686 // Validate the SYSm value first. 4687 switch (ValLow) { 4688 case 0: // apsr 4689 case 1: // iapsr 4690 case 2: // eapsr 4691 case 3: // xpsr 4692 case 5: // ipsr 4693 case 6: // epsr 4694 case 7: // iepsr 4695 case 8: // msp 4696 case 9: // psp 4697 case 16: // primask 4698 case 20: // control 4699 break; 4700 case 17: // basepri 4701 case 18: // basepri_max 4702 case 19: // faultmask 4703 if (!(FeatureBits[ARM::HasV7Ops])) 4704 // Values basepri, basepri_max and faultmask are only valid for v7m. 4705 return MCDisassembler::Fail; 4706 break; 4707 case 0x8a: // msplim_ns 4708 case 0x8b: // psplim_ns 4709 case 0x91: // basepri_ns 4710 case 0x93: // faultmask_ns 4711 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4712 return MCDisassembler::Fail; 4713 LLVM_FALLTHROUGH; 4714 case 10: // msplim 4715 case 11: // psplim 4716 case 0x88: // msp_ns 4717 case 0x89: // psp_ns 4718 case 0x90: // primask_ns 4719 case 0x94: // control_ns 4720 case 0x98: // sp_ns 4721 if (!(FeatureBits[ARM::Feature8MSecExt])) 4722 return MCDisassembler::Fail; 4723 break; 4724 default: 4725 // Architecturally defined as unpredictable 4726 S = MCDisassembler::SoftFail; 4727 break; 4728 } 4729 4730 if (Inst.getOpcode() == ARM::t2MSR_M) { 4731 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4732 if (!(FeatureBits[ARM::HasV7Ops])) { 4733 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4734 // unpredictable. 4735 if (Mask != 2) 4736 S = MCDisassembler::SoftFail; 4737 } 4738 else { 4739 // The ARMv7-M architecture stores an additional 2-bit mask value in 4740 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4741 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4742 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4743 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4744 // only if the processor includes the DSP extension. 4745 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4746 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4747 S = MCDisassembler::SoftFail; 4748 } 4749 } 4750 } else { 4751 // A/R class 4752 if (Val == 0) 4753 return MCDisassembler::Fail; 4754 } 4755 Inst.addOperand(MCOperand::createImm(Val)); 4756 return S; 4757 } 4758 4759 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4760 uint64_t Address, const void *Decoder) { 4761 unsigned R = fieldFromInstruction(Val, 5, 1); 4762 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4763 4764 // The table of encodings for these banked registers comes from B9.2.3 of the 4765 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4766 // neater. So by fiat, these values are UNPREDICTABLE: 4767 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4768 return MCDisassembler::Fail; 4769 4770 Inst.addOperand(MCOperand::createImm(Val)); 4771 return MCDisassembler::Success; 4772 } 4773 4774 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4775 uint64_t Address, const void *Decoder) { 4776 DecodeStatus S = MCDisassembler::Success; 4777 4778 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4779 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4780 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4781 4782 if (Rn == 0xF) 4783 S = MCDisassembler::SoftFail; 4784 4785 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4786 return MCDisassembler::Fail; 4787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4788 return MCDisassembler::Fail; 4789 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4790 return MCDisassembler::Fail; 4791 4792 return S; 4793 } 4794 4795 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4796 uint64_t Address, 4797 const void *Decoder) { 4798 DecodeStatus S = MCDisassembler::Success; 4799 4800 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4801 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4802 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4803 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4804 4805 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4806 return MCDisassembler::Fail; 4807 4808 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4809 S = MCDisassembler::SoftFail; 4810 4811 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4812 return MCDisassembler::Fail; 4813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4814 return MCDisassembler::Fail; 4815 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4816 return MCDisassembler::Fail; 4817 4818 return S; 4819 } 4820 4821 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4822 uint64_t Address, const void *Decoder) { 4823 DecodeStatus S = MCDisassembler::Success; 4824 4825 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4826 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4827 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4828 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4829 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4830 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4831 4832 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4833 4834 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4835 return MCDisassembler::Fail; 4836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4837 return MCDisassembler::Fail; 4838 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4839 return MCDisassembler::Fail; 4840 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4841 return MCDisassembler::Fail; 4842 4843 return S; 4844 } 4845 4846 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4847 uint64_t Address, const void *Decoder) { 4848 DecodeStatus S = MCDisassembler::Success; 4849 4850 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4851 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4852 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4853 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4854 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4855 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4856 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4857 4858 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4859 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4860 4861 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4862 return MCDisassembler::Fail; 4863 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4864 return MCDisassembler::Fail; 4865 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4866 return MCDisassembler::Fail; 4867 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4868 return MCDisassembler::Fail; 4869 4870 return S; 4871 } 4872 4873 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4874 uint64_t Address, const void *Decoder) { 4875 DecodeStatus S = MCDisassembler::Success; 4876 4877 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4878 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4879 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4880 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4881 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4882 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4883 4884 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4885 4886 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4887 return MCDisassembler::Fail; 4888 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4889 return MCDisassembler::Fail; 4890 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4891 return MCDisassembler::Fail; 4892 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4893 return MCDisassembler::Fail; 4894 4895 return S; 4896 } 4897 4898 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4899 uint64_t Address, const void *Decoder) { 4900 DecodeStatus S = MCDisassembler::Success; 4901 4902 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4903 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4904 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4905 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4906 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4907 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4908 4909 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4910 4911 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4912 return MCDisassembler::Fail; 4913 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4914 return MCDisassembler::Fail; 4915 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4916 return MCDisassembler::Fail; 4917 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4918 return MCDisassembler::Fail; 4919 4920 return S; 4921 } 4922 4923 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4924 uint64_t Address, const void *Decoder) { 4925 DecodeStatus S = MCDisassembler::Success; 4926 4927 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4928 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4929 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4930 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4931 unsigned size = fieldFromInstruction(Insn, 10, 2); 4932 4933 unsigned align = 0; 4934 unsigned index = 0; 4935 switch (size) { 4936 default: 4937 return MCDisassembler::Fail; 4938 case 0: 4939 if (fieldFromInstruction(Insn, 4, 1)) 4940 return MCDisassembler::Fail; // UNDEFINED 4941 index = fieldFromInstruction(Insn, 5, 3); 4942 break; 4943 case 1: 4944 if (fieldFromInstruction(Insn, 5, 1)) 4945 return MCDisassembler::Fail; // UNDEFINED 4946 index = fieldFromInstruction(Insn, 6, 2); 4947 if (fieldFromInstruction(Insn, 4, 1)) 4948 align = 2; 4949 break; 4950 case 2: 4951 if (fieldFromInstruction(Insn, 6, 1)) 4952 return MCDisassembler::Fail; // UNDEFINED 4953 index = fieldFromInstruction(Insn, 7, 1); 4954 4955 switch (fieldFromInstruction(Insn, 4, 2)) { 4956 case 0 : 4957 align = 0; break; 4958 case 3: 4959 align = 4; break; 4960 default: 4961 return MCDisassembler::Fail; 4962 } 4963 break; 4964 } 4965 4966 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4967 return MCDisassembler::Fail; 4968 if (Rm != 0xF) { // Writeback 4969 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4970 return MCDisassembler::Fail; 4971 } 4972 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4973 return MCDisassembler::Fail; 4974 Inst.addOperand(MCOperand::createImm(align)); 4975 if (Rm != 0xF) { 4976 if (Rm != 0xD) { 4977 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4978 return MCDisassembler::Fail; 4979 } else 4980 Inst.addOperand(MCOperand::createReg(0)); 4981 } 4982 4983 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4984 return MCDisassembler::Fail; 4985 Inst.addOperand(MCOperand::createImm(index)); 4986 4987 return S; 4988 } 4989 4990 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4991 uint64_t Address, const void *Decoder) { 4992 DecodeStatus S = MCDisassembler::Success; 4993 4994 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4995 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4996 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4997 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4998 unsigned size = fieldFromInstruction(Insn, 10, 2); 4999 5000 unsigned align = 0; 5001 unsigned index = 0; 5002 switch (size) { 5003 default: 5004 return MCDisassembler::Fail; 5005 case 0: 5006 if (fieldFromInstruction(Insn, 4, 1)) 5007 return MCDisassembler::Fail; // UNDEFINED 5008 index = fieldFromInstruction(Insn, 5, 3); 5009 break; 5010 case 1: 5011 if (fieldFromInstruction(Insn, 5, 1)) 5012 return MCDisassembler::Fail; // UNDEFINED 5013 index = fieldFromInstruction(Insn, 6, 2); 5014 if (fieldFromInstruction(Insn, 4, 1)) 5015 align = 2; 5016 break; 5017 case 2: 5018 if (fieldFromInstruction(Insn, 6, 1)) 5019 return MCDisassembler::Fail; // UNDEFINED 5020 index = fieldFromInstruction(Insn, 7, 1); 5021 5022 switch (fieldFromInstruction(Insn, 4, 2)) { 5023 case 0: 5024 align = 0; break; 5025 case 3: 5026 align = 4; break; 5027 default: 5028 return MCDisassembler::Fail; 5029 } 5030 break; 5031 } 5032 5033 if (Rm != 0xF) { // Writeback 5034 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5035 return MCDisassembler::Fail; 5036 } 5037 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5038 return MCDisassembler::Fail; 5039 Inst.addOperand(MCOperand::createImm(align)); 5040 if (Rm != 0xF) { 5041 if (Rm != 0xD) { 5042 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5043 return MCDisassembler::Fail; 5044 } else 5045 Inst.addOperand(MCOperand::createReg(0)); 5046 } 5047 5048 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5049 return MCDisassembler::Fail; 5050 Inst.addOperand(MCOperand::createImm(index)); 5051 5052 return S; 5053 } 5054 5055 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 5056 uint64_t Address, const void *Decoder) { 5057 DecodeStatus S = MCDisassembler::Success; 5058 5059 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5060 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5061 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5062 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5063 unsigned size = fieldFromInstruction(Insn, 10, 2); 5064 5065 unsigned align = 0; 5066 unsigned index = 0; 5067 unsigned inc = 1; 5068 switch (size) { 5069 default: 5070 return MCDisassembler::Fail; 5071 case 0: 5072 index = fieldFromInstruction(Insn, 5, 3); 5073 if (fieldFromInstruction(Insn, 4, 1)) 5074 align = 2; 5075 break; 5076 case 1: 5077 index = fieldFromInstruction(Insn, 6, 2); 5078 if (fieldFromInstruction(Insn, 4, 1)) 5079 align = 4; 5080 if (fieldFromInstruction(Insn, 5, 1)) 5081 inc = 2; 5082 break; 5083 case 2: 5084 if (fieldFromInstruction(Insn, 5, 1)) 5085 return MCDisassembler::Fail; // UNDEFINED 5086 index = fieldFromInstruction(Insn, 7, 1); 5087 if (fieldFromInstruction(Insn, 4, 1) != 0) 5088 align = 8; 5089 if (fieldFromInstruction(Insn, 6, 1)) 5090 inc = 2; 5091 break; 5092 } 5093 5094 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5095 return MCDisassembler::Fail; 5096 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5097 return MCDisassembler::Fail; 5098 if (Rm != 0xF) { // Writeback 5099 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5100 return MCDisassembler::Fail; 5101 } 5102 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5103 return MCDisassembler::Fail; 5104 Inst.addOperand(MCOperand::createImm(align)); 5105 if (Rm != 0xF) { 5106 if (Rm != 0xD) { 5107 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5108 return MCDisassembler::Fail; 5109 } else 5110 Inst.addOperand(MCOperand::createReg(0)); 5111 } 5112 5113 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5114 return MCDisassembler::Fail; 5115 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5116 return MCDisassembler::Fail; 5117 Inst.addOperand(MCOperand::createImm(index)); 5118 5119 return S; 5120 } 5121 5122 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 5123 uint64_t Address, const void *Decoder) { 5124 DecodeStatus S = MCDisassembler::Success; 5125 5126 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5127 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5128 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5129 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5130 unsigned size = fieldFromInstruction(Insn, 10, 2); 5131 5132 unsigned align = 0; 5133 unsigned index = 0; 5134 unsigned inc = 1; 5135 switch (size) { 5136 default: 5137 return MCDisassembler::Fail; 5138 case 0: 5139 index = fieldFromInstruction(Insn, 5, 3); 5140 if (fieldFromInstruction(Insn, 4, 1)) 5141 align = 2; 5142 break; 5143 case 1: 5144 index = fieldFromInstruction(Insn, 6, 2); 5145 if (fieldFromInstruction(Insn, 4, 1)) 5146 align = 4; 5147 if (fieldFromInstruction(Insn, 5, 1)) 5148 inc = 2; 5149 break; 5150 case 2: 5151 if (fieldFromInstruction(Insn, 5, 1)) 5152 return MCDisassembler::Fail; // UNDEFINED 5153 index = fieldFromInstruction(Insn, 7, 1); 5154 if (fieldFromInstruction(Insn, 4, 1) != 0) 5155 align = 8; 5156 if (fieldFromInstruction(Insn, 6, 1)) 5157 inc = 2; 5158 break; 5159 } 5160 5161 if (Rm != 0xF) { // Writeback 5162 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5163 return MCDisassembler::Fail; 5164 } 5165 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5166 return MCDisassembler::Fail; 5167 Inst.addOperand(MCOperand::createImm(align)); 5168 if (Rm != 0xF) { 5169 if (Rm != 0xD) { 5170 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5171 return MCDisassembler::Fail; 5172 } else 5173 Inst.addOperand(MCOperand::createReg(0)); 5174 } 5175 5176 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5177 return MCDisassembler::Fail; 5178 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5179 return MCDisassembler::Fail; 5180 Inst.addOperand(MCOperand::createImm(index)); 5181 5182 return S; 5183 } 5184 5185 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 5186 uint64_t Address, const void *Decoder) { 5187 DecodeStatus S = MCDisassembler::Success; 5188 5189 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5190 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5191 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5192 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5193 unsigned size = fieldFromInstruction(Insn, 10, 2); 5194 5195 unsigned align = 0; 5196 unsigned index = 0; 5197 unsigned inc = 1; 5198 switch (size) { 5199 default: 5200 return MCDisassembler::Fail; 5201 case 0: 5202 if (fieldFromInstruction(Insn, 4, 1)) 5203 return MCDisassembler::Fail; // UNDEFINED 5204 index = fieldFromInstruction(Insn, 5, 3); 5205 break; 5206 case 1: 5207 if (fieldFromInstruction(Insn, 4, 1)) 5208 return MCDisassembler::Fail; // UNDEFINED 5209 index = fieldFromInstruction(Insn, 6, 2); 5210 if (fieldFromInstruction(Insn, 5, 1)) 5211 inc = 2; 5212 break; 5213 case 2: 5214 if (fieldFromInstruction(Insn, 4, 2)) 5215 return MCDisassembler::Fail; // UNDEFINED 5216 index = fieldFromInstruction(Insn, 7, 1); 5217 if (fieldFromInstruction(Insn, 6, 1)) 5218 inc = 2; 5219 break; 5220 } 5221 5222 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5223 return MCDisassembler::Fail; 5224 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5225 return MCDisassembler::Fail; 5226 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5227 return MCDisassembler::Fail; 5228 5229 if (Rm != 0xF) { // Writeback 5230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5231 return MCDisassembler::Fail; 5232 } 5233 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5234 return MCDisassembler::Fail; 5235 Inst.addOperand(MCOperand::createImm(align)); 5236 if (Rm != 0xF) { 5237 if (Rm != 0xD) { 5238 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5239 return MCDisassembler::Fail; 5240 } else 5241 Inst.addOperand(MCOperand::createReg(0)); 5242 } 5243 5244 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5245 return MCDisassembler::Fail; 5246 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5247 return MCDisassembler::Fail; 5248 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5249 return MCDisassembler::Fail; 5250 Inst.addOperand(MCOperand::createImm(index)); 5251 5252 return S; 5253 } 5254 5255 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5256 uint64_t Address, const void *Decoder) { 5257 DecodeStatus S = MCDisassembler::Success; 5258 5259 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5260 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5261 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5262 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5263 unsigned size = fieldFromInstruction(Insn, 10, 2); 5264 5265 unsigned align = 0; 5266 unsigned index = 0; 5267 unsigned inc = 1; 5268 switch (size) { 5269 default: 5270 return MCDisassembler::Fail; 5271 case 0: 5272 if (fieldFromInstruction(Insn, 4, 1)) 5273 return MCDisassembler::Fail; // UNDEFINED 5274 index = fieldFromInstruction(Insn, 5, 3); 5275 break; 5276 case 1: 5277 if (fieldFromInstruction(Insn, 4, 1)) 5278 return MCDisassembler::Fail; // UNDEFINED 5279 index = fieldFromInstruction(Insn, 6, 2); 5280 if (fieldFromInstruction(Insn, 5, 1)) 5281 inc = 2; 5282 break; 5283 case 2: 5284 if (fieldFromInstruction(Insn, 4, 2)) 5285 return MCDisassembler::Fail; // UNDEFINED 5286 index = fieldFromInstruction(Insn, 7, 1); 5287 if (fieldFromInstruction(Insn, 6, 1)) 5288 inc = 2; 5289 break; 5290 } 5291 5292 if (Rm != 0xF) { // Writeback 5293 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5294 return MCDisassembler::Fail; 5295 } 5296 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5297 return MCDisassembler::Fail; 5298 Inst.addOperand(MCOperand::createImm(align)); 5299 if (Rm != 0xF) { 5300 if (Rm != 0xD) { 5301 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5302 return MCDisassembler::Fail; 5303 } else 5304 Inst.addOperand(MCOperand::createReg(0)); 5305 } 5306 5307 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5308 return MCDisassembler::Fail; 5309 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5310 return MCDisassembler::Fail; 5311 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5312 return MCDisassembler::Fail; 5313 Inst.addOperand(MCOperand::createImm(index)); 5314 5315 return S; 5316 } 5317 5318 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5319 uint64_t Address, const void *Decoder) { 5320 DecodeStatus S = MCDisassembler::Success; 5321 5322 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5323 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5324 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5325 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5326 unsigned size = fieldFromInstruction(Insn, 10, 2); 5327 5328 unsigned align = 0; 5329 unsigned index = 0; 5330 unsigned inc = 1; 5331 switch (size) { 5332 default: 5333 return MCDisassembler::Fail; 5334 case 0: 5335 if (fieldFromInstruction(Insn, 4, 1)) 5336 align = 4; 5337 index = fieldFromInstruction(Insn, 5, 3); 5338 break; 5339 case 1: 5340 if (fieldFromInstruction(Insn, 4, 1)) 5341 align = 8; 5342 index = fieldFromInstruction(Insn, 6, 2); 5343 if (fieldFromInstruction(Insn, 5, 1)) 5344 inc = 2; 5345 break; 5346 case 2: 5347 switch (fieldFromInstruction(Insn, 4, 2)) { 5348 case 0: 5349 align = 0; break; 5350 case 3: 5351 return MCDisassembler::Fail; 5352 default: 5353 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5354 } 5355 5356 index = fieldFromInstruction(Insn, 7, 1); 5357 if (fieldFromInstruction(Insn, 6, 1)) 5358 inc = 2; 5359 break; 5360 } 5361 5362 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5363 return MCDisassembler::Fail; 5364 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5365 return MCDisassembler::Fail; 5366 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5367 return MCDisassembler::Fail; 5368 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5369 return MCDisassembler::Fail; 5370 5371 if (Rm != 0xF) { // Writeback 5372 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5373 return MCDisassembler::Fail; 5374 } 5375 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5376 return MCDisassembler::Fail; 5377 Inst.addOperand(MCOperand::createImm(align)); 5378 if (Rm != 0xF) { 5379 if (Rm != 0xD) { 5380 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5381 return MCDisassembler::Fail; 5382 } else 5383 Inst.addOperand(MCOperand::createReg(0)); 5384 } 5385 5386 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5387 return MCDisassembler::Fail; 5388 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5389 return MCDisassembler::Fail; 5390 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5391 return MCDisassembler::Fail; 5392 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5393 return MCDisassembler::Fail; 5394 Inst.addOperand(MCOperand::createImm(index)); 5395 5396 return S; 5397 } 5398 5399 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5400 uint64_t Address, const void *Decoder) { 5401 DecodeStatus S = MCDisassembler::Success; 5402 5403 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5404 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5405 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5406 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5407 unsigned size = fieldFromInstruction(Insn, 10, 2); 5408 5409 unsigned align = 0; 5410 unsigned index = 0; 5411 unsigned inc = 1; 5412 switch (size) { 5413 default: 5414 return MCDisassembler::Fail; 5415 case 0: 5416 if (fieldFromInstruction(Insn, 4, 1)) 5417 align = 4; 5418 index = fieldFromInstruction(Insn, 5, 3); 5419 break; 5420 case 1: 5421 if (fieldFromInstruction(Insn, 4, 1)) 5422 align = 8; 5423 index = fieldFromInstruction(Insn, 6, 2); 5424 if (fieldFromInstruction(Insn, 5, 1)) 5425 inc = 2; 5426 break; 5427 case 2: 5428 switch (fieldFromInstruction(Insn, 4, 2)) { 5429 case 0: 5430 align = 0; break; 5431 case 3: 5432 return MCDisassembler::Fail; 5433 default: 5434 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5435 } 5436 5437 index = fieldFromInstruction(Insn, 7, 1); 5438 if (fieldFromInstruction(Insn, 6, 1)) 5439 inc = 2; 5440 break; 5441 } 5442 5443 if (Rm != 0xF) { // Writeback 5444 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5445 return MCDisassembler::Fail; 5446 } 5447 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5448 return MCDisassembler::Fail; 5449 Inst.addOperand(MCOperand::createImm(align)); 5450 if (Rm != 0xF) { 5451 if (Rm != 0xD) { 5452 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5453 return MCDisassembler::Fail; 5454 } else 5455 Inst.addOperand(MCOperand::createReg(0)); 5456 } 5457 5458 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5459 return MCDisassembler::Fail; 5460 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5461 return MCDisassembler::Fail; 5462 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5463 return MCDisassembler::Fail; 5464 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5465 return MCDisassembler::Fail; 5466 Inst.addOperand(MCOperand::createImm(index)); 5467 5468 return S; 5469 } 5470 5471 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5472 uint64_t Address, const void *Decoder) { 5473 DecodeStatus S = MCDisassembler::Success; 5474 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5475 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5476 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5477 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5478 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5479 5480 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5481 S = MCDisassembler::SoftFail; 5482 5483 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5484 return MCDisassembler::Fail; 5485 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5486 return MCDisassembler::Fail; 5487 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5488 return MCDisassembler::Fail; 5489 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5490 return MCDisassembler::Fail; 5491 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5492 return MCDisassembler::Fail; 5493 5494 return S; 5495 } 5496 5497 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5498 uint64_t Address, const void *Decoder) { 5499 DecodeStatus S = MCDisassembler::Success; 5500 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5501 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5502 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5503 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5504 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5505 5506 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5507 S = MCDisassembler::SoftFail; 5508 5509 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5510 return MCDisassembler::Fail; 5511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5512 return MCDisassembler::Fail; 5513 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5514 return MCDisassembler::Fail; 5515 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5516 return MCDisassembler::Fail; 5517 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5518 return MCDisassembler::Fail; 5519 5520 return S; 5521 } 5522 5523 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5524 uint64_t Address, const void *Decoder) { 5525 DecodeStatus S = MCDisassembler::Success; 5526 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5527 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5528 5529 if (pred == 0xF) { 5530 pred = 0xE; 5531 S = MCDisassembler::SoftFail; 5532 } 5533 5534 if (mask == 0x0) 5535 return MCDisassembler::Fail; 5536 5537 // IT masks are encoded as a sequence of replacement low-order bits 5538 // for the condition code. So if the low bit of the starting 5539 // condition code is 1, then we have to flip all the bits above the 5540 // terminating bit (which is the lowest 1 bit). 5541 if (pred & 1) { 5542 unsigned LowBit = mask & -mask; 5543 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5544 mask ^= BitsAboveLowBit; 5545 } 5546 5547 Inst.addOperand(MCOperand::createImm(pred)); 5548 Inst.addOperand(MCOperand::createImm(mask)); 5549 return S; 5550 } 5551 5552 static DecodeStatus 5553 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5554 uint64_t Address, const void *Decoder) { 5555 DecodeStatus S = MCDisassembler::Success; 5556 5557 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5558 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5559 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5560 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5561 unsigned W = fieldFromInstruction(Insn, 21, 1); 5562 unsigned U = fieldFromInstruction(Insn, 23, 1); 5563 unsigned P = fieldFromInstruction(Insn, 24, 1); 5564 bool writeback = (W == 1) | (P == 0); 5565 5566 addr |= (U << 8) | (Rn << 9); 5567 5568 if (writeback && (Rn == Rt || Rn == Rt2)) 5569 Check(S, MCDisassembler::SoftFail); 5570 if (Rt == Rt2) 5571 Check(S, MCDisassembler::SoftFail); 5572 5573 // Rt 5574 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5575 return MCDisassembler::Fail; 5576 // Rt2 5577 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5578 return MCDisassembler::Fail; 5579 // Writeback operand 5580 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5581 return MCDisassembler::Fail; 5582 // addr 5583 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5584 return MCDisassembler::Fail; 5585 5586 return S; 5587 } 5588 5589 static DecodeStatus 5590 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5591 uint64_t Address, const void *Decoder) { 5592 DecodeStatus S = MCDisassembler::Success; 5593 5594 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5595 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5596 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5597 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5598 unsigned W = fieldFromInstruction(Insn, 21, 1); 5599 unsigned U = fieldFromInstruction(Insn, 23, 1); 5600 unsigned P = fieldFromInstruction(Insn, 24, 1); 5601 bool writeback = (W == 1) | (P == 0); 5602 5603 addr |= (U << 8) | (Rn << 9); 5604 5605 if (writeback && (Rn == Rt || Rn == Rt2)) 5606 Check(S, MCDisassembler::SoftFail); 5607 5608 // Writeback operand 5609 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5610 return MCDisassembler::Fail; 5611 // Rt 5612 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5613 return MCDisassembler::Fail; 5614 // Rt2 5615 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5616 return MCDisassembler::Fail; 5617 // addr 5618 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5619 return MCDisassembler::Fail; 5620 5621 return S; 5622 } 5623 5624 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5625 uint64_t Address, const void *Decoder) { 5626 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5627 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5628 if (sign1 != sign2) return MCDisassembler::Fail; 5629 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 5630 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); 5631 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); 5632 5633 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5634 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5635 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5636 // If sign, then it is decreasing the address. 5637 if (sign1) { 5638 // Following ARMv7 Architecture Manual, when the offset 5639 // is zero, it is decoded as a subw, not as a adr.w 5640 if (!Val) { 5641 Inst.setOpcode(ARM::t2SUBri12); 5642 Inst.addOperand(MCOperand::createReg(ARM::PC)); 5643 } else 5644 Val = -Val; 5645 } 5646 Inst.addOperand(MCOperand::createImm(Val)); 5647 return S; 5648 } 5649 5650 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5651 uint64_t Address, 5652 const void *Decoder) { 5653 DecodeStatus S = MCDisassembler::Success; 5654 5655 // Shift of "asr #32" is not allowed in Thumb2 mode. 5656 if (Val == 0x20) S = MCDisassembler::Fail; 5657 Inst.addOperand(MCOperand::createImm(Val)); 5658 return S; 5659 } 5660 5661 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5662 uint64_t Address, const void *Decoder) { 5663 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5664 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5665 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5666 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5667 5668 if (pred == 0xF) 5669 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5670 5671 DecodeStatus S = MCDisassembler::Success; 5672 5673 if (Rt == Rn || Rn == Rt2) 5674 S = MCDisassembler::SoftFail; 5675 5676 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5677 return MCDisassembler::Fail; 5678 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5679 return MCDisassembler::Fail; 5680 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5681 return MCDisassembler::Fail; 5682 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5683 return MCDisassembler::Fail; 5684 5685 return S; 5686 } 5687 5688 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5689 uint64_t Address, const void *Decoder) { 5690 const FeatureBitset &featureBits = 5691 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5692 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5693 5694 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5695 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5696 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5697 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5698 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5699 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5700 unsigned op = fieldFromInstruction(Insn, 5, 1); 5701 5702 DecodeStatus S = MCDisassembler::Success; 5703 5704 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5705 if (!(imm & 0x38)) { 5706 if (cmode == 0xF) { 5707 if (op == 1) return MCDisassembler::Fail; 5708 Inst.setOpcode(ARM::VMOVv2f32); 5709 } 5710 if (hasFullFP16) { 5711 if (cmode == 0xE) { 5712 if (op == 1) { 5713 Inst.setOpcode(ARM::VMOVv1i64); 5714 } else { 5715 Inst.setOpcode(ARM::VMOVv8i8); 5716 } 5717 } 5718 if (cmode == 0xD) { 5719 if (op == 1) { 5720 Inst.setOpcode(ARM::VMVNv2i32); 5721 } else { 5722 Inst.setOpcode(ARM::VMOVv2i32); 5723 } 5724 } 5725 if (cmode == 0xC) { 5726 if (op == 1) { 5727 Inst.setOpcode(ARM::VMVNv2i32); 5728 } else { 5729 Inst.setOpcode(ARM::VMOVv2i32); 5730 } 5731 } 5732 } 5733 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5734 } 5735 5736 if (!(imm & 0x20)) return MCDisassembler::Fail; 5737 5738 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5739 return MCDisassembler::Fail; 5740 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5741 return MCDisassembler::Fail; 5742 Inst.addOperand(MCOperand::createImm(64 - imm)); 5743 5744 return S; 5745 } 5746 5747 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5748 uint64_t Address, const void *Decoder) { 5749 const FeatureBitset &featureBits = 5750 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5751 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5752 5753 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5754 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5755 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5756 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5757 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5758 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5759 unsigned op = fieldFromInstruction(Insn, 5, 1); 5760 5761 DecodeStatus S = MCDisassembler::Success; 5762 5763 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5764 if (!(imm & 0x38)) { 5765 if (cmode == 0xF) { 5766 if (op == 1) return MCDisassembler::Fail; 5767 Inst.setOpcode(ARM::VMOVv4f32); 5768 } 5769 if (hasFullFP16) { 5770 if (cmode == 0xE) { 5771 if (op == 1) { 5772 Inst.setOpcode(ARM::VMOVv2i64); 5773 } else { 5774 Inst.setOpcode(ARM::VMOVv16i8); 5775 } 5776 } 5777 if (cmode == 0xD) { 5778 if (op == 1) { 5779 Inst.setOpcode(ARM::VMVNv4i32); 5780 } else { 5781 Inst.setOpcode(ARM::VMOVv4i32); 5782 } 5783 } 5784 if (cmode == 0xC) { 5785 if (op == 1) { 5786 Inst.setOpcode(ARM::VMVNv4i32); 5787 } else { 5788 Inst.setOpcode(ARM::VMOVv4i32); 5789 } 5790 } 5791 } 5792 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5793 } 5794 5795 if (!(imm & 0x20)) return MCDisassembler::Fail; 5796 5797 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5798 return MCDisassembler::Fail; 5799 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5800 return MCDisassembler::Fail; 5801 Inst.addOperand(MCOperand::createImm(64 - imm)); 5802 5803 return S; 5804 } 5805 5806 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5807 unsigned Insn, 5808 uint64_t Address, 5809 const void *Decoder) { 5810 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5811 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5812 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5813 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5814 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5815 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5816 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5817 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5818 5819 DecodeStatus S = MCDisassembler::Success; 5820 5821 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5822 5823 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5824 return MCDisassembler::Fail; 5825 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5826 return MCDisassembler::Fail; 5827 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5828 return MCDisassembler::Fail; 5829 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5830 return MCDisassembler::Fail; 5831 // The lane index does not have any bits in the encoding, because it can only 5832 // be 0. 5833 Inst.addOperand(MCOperand::createImm(0)); 5834 Inst.addOperand(MCOperand::createImm(rotate)); 5835 5836 return S; 5837 } 5838 5839 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5840 uint64_t Address, const void *Decoder) { 5841 DecodeStatus S = MCDisassembler::Success; 5842 5843 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5844 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5845 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5846 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5847 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5848 5849 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5850 S = MCDisassembler::SoftFail; 5851 5852 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5853 return MCDisassembler::Fail; 5854 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5855 return MCDisassembler::Fail; 5856 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5857 return MCDisassembler::Fail; 5858 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5859 return MCDisassembler::Fail; 5860 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5861 return MCDisassembler::Fail; 5862 5863 return S; 5864 } 5865 5866 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5867 uint64_t Address, const void *Decoder) { 5868 DecodeStatus S = MCDisassembler::Success; 5869 5870 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5871 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5872 unsigned cop = fieldFromInstruction(Val, 8, 4); 5873 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5874 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5875 5876 if ((cop & ~0x1) == 0xa) 5877 return MCDisassembler::Fail; 5878 5879 if (Rt == Rt2) 5880 S = MCDisassembler::SoftFail; 5881 5882 // We have to check if the instruction is MRRC2 5883 // or MCRR2 when constructing the operands for 5884 // Inst. Reason is because MRRC2 stores to two 5885 // registers so it's tablegen desc has has two 5886 // outputs whereas MCRR doesn't store to any 5887 // registers so all of it's operands are listed 5888 // as inputs, therefore the operand order for 5889 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5890 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5891 5892 if (Inst.getOpcode() == ARM::MRRC2) { 5893 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5894 return MCDisassembler::Fail; 5895 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5896 return MCDisassembler::Fail; 5897 } 5898 Inst.addOperand(MCOperand::createImm(cop)); 5899 Inst.addOperand(MCOperand::createImm(opc1)); 5900 if (Inst.getOpcode() == ARM::MCRR2) { 5901 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5902 return MCDisassembler::Fail; 5903 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5904 return MCDisassembler::Fail; 5905 } 5906 Inst.addOperand(MCOperand::createImm(CRm)); 5907 5908 return S; 5909 } 5910 5911 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5912 uint64_t Address, 5913 const void *Decoder) { 5914 const FeatureBitset &featureBits = 5915 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5916 DecodeStatus S = MCDisassembler::Success; 5917 5918 // Add explicit operand for the destination sysreg, for cases where 5919 // we have to model it for code generation purposes. 5920 switch (Inst.getOpcode()) { 5921 case ARM::VMSR_FPSCR_NZCVQC: 5922 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5923 break; 5924 case ARM::VMSR_P0: 5925 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5926 break; 5927 } 5928 5929 if (Inst.getOpcode() != ARM::FMSTAT) { 5930 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5931 5932 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5933 if (Rt == 13 || Rt == 15) 5934 S = MCDisassembler::SoftFail; 5935 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5936 } else 5937 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5938 } 5939 5940 // Add explicit operand for the source sysreg, similarly to above. 5941 switch (Inst.getOpcode()) { 5942 case ARM::VMRS_FPSCR_NZCVQC: 5943 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5944 break; 5945 case ARM::VMRS_P0: 5946 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5947 break; 5948 } 5949 5950 if (featureBits[ARM::ModeThumb]) { 5951 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5952 Inst.addOperand(MCOperand::createReg(0)); 5953 } else { 5954 unsigned pred = fieldFromInstruction(Val, 28, 4); 5955 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5956 return MCDisassembler::Fail; 5957 } 5958 5959 return S; 5960 } 5961 5962 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 5963 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5964 uint64_t Address, 5965 const void *Decoder) { 5966 DecodeStatus S = MCDisassembler::Success; 5967 if (Val == 0 && !zeroPermitted) 5968 S = MCDisassembler::Fail; 5969 5970 uint64_t DecVal; 5971 if (isSigned) 5972 DecVal = SignExtend32<size + 1>(Val << 1); 5973 else 5974 DecVal = (Val << 1); 5975 5976 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5977 Decoder)) 5978 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5979 return S; 5980 } 5981 5982 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5983 uint64_t Address, 5984 const void *Decoder) { 5985 5986 uint64_t LocImm = Inst.getOperand(0).getImm(); 5987 Val = LocImm + (2 << Val); 5988 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5989 Decoder)) 5990 Inst.addOperand(MCOperand::createImm(Val)); 5991 return MCDisassembler::Success; 5992 } 5993 5994 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5995 uint64_t Address, 5996 const void *Decoder) { 5997 if (Val >= ARMCC::AL) // also exclude the non-condition NV 5998 return MCDisassembler::Fail; 5999 Inst.addOperand(MCOperand::createImm(Val)); 6000 return MCDisassembler::Success; 6001 } 6002 6003 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 6004 const void *Decoder) { 6005 DecodeStatus S = MCDisassembler::Success; 6006 6007 if (Inst.getOpcode() == ARM::MVE_LCTP) 6008 return S; 6009 6010 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 6011 fieldFromInstruction(Insn, 1, 10) << 1; 6012 switch (Inst.getOpcode()) { 6013 case ARM::t2LEUpdate: 6014 case ARM::MVE_LETP: 6015 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6016 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6017 LLVM_FALLTHROUGH; 6018 case ARM::t2LE: 6019 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>( 6020 Inst, Imm, Address, Decoder))) 6021 return MCDisassembler::Fail; 6022 break; 6023 case ARM::t2WLS: 6024 case ARM::MVE_WLSTP_8: 6025 case ARM::MVE_WLSTP_16: 6026 case ARM::MVE_WLSTP_32: 6027 case ARM::MVE_WLSTP_64: 6028 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6029 if (!Check(S, 6030 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 6031 Address, Decoder)) || 6032 !Check(S, DecodeBFLabelOperand<false, false, true, 11>( 6033 Inst, Imm, Address, Decoder))) 6034 return MCDisassembler::Fail; 6035 break; 6036 case ARM::t2DLS: 6037 case ARM::MVE_DLSTP_8: 6038 case ARM::MVE_DLSTP_16: 6039 case ARM::MVE_DLSTP_32: 6040 case ARM::MVE_DLSTP_64: 6041 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6042 if (Rn == 0xF) { 6043 // Enforce all the rest of the instruction bits in LCTP, which 6044 // won't have been reliably checked based on LCTP's own tablegen 6045 // record, because we came to this decode by a roundabout route. 6046 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 6047 if ((Insn & ~SBZMask) != CanonicalLCTP) 6048 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 6049 if (Insn != CanonicalLCTP) 6050 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 6051 6052 Inst.setOpcode(ARM::MVE_LCTP); 6053 } else { 6054 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6055 if (!Check(S, DecoderGPRRegisterClass(Inst, 6056 fieldFromInstruction(Insn, 16, 4), 6057 Address, Decoder))) 6058 return MCDisassembler::Fail; 6059 } 6060 break; 6061 } 6062 return S; 6063 } 6064 6065 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6066 uint64_t Address, 6067 const void *Decoder) { 6068 DecodeStatus S = MCDisassembler::Success; 6069 6070 if (Val == 0) 6071 Val = 32; 6072 6073 Inst.addOperand(MCOperand::createImm(Val)); 6074 6075 return S; 6076 } 6077 6078 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6079 uint64_t Address, const void *Decoder) { 6080 if ((RegNo) + 1 > 11) 6081 return MCDisassembler::Fail; 6082 6083 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6084 Inst.addOperand(MCOperand::createReg(Register)); 6085 return MCDisassembler::Success; 6086 } 6087 6088 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6089 uint64_t Address, const void *Decoder) { 6090 if ((RegNo) > 14) 6091 return MCDisassembler::Fail; 6092 6093 unsigned Register = GPRDecoderTable[(RegNo)]; 6094 Inst.addOperand(MCOperand::createReg(Register)); 6095 return MCDisassembler::Success; 6096 } 6097 6098 static DecodeStatus 6099 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 6100 uint64_t Address, const void *Decoder) { 6101 if (RegNo == 15) { 6102 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 6103 return MCDisassembler::Success; 6104 } 6105 6106 unsigned Register = GPRDecoderTable[RegNo]; 6107 Inst.addOperand(MCOperand::createReg(Register)); 6108 6109 if (RegNo == 13) 6110 return MCDisassembler::SoftFail; 6111 6112 return MCDisassembler::Success; 6113 } 6114 6115 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6116 const void *Decoder) { 6117 DecodeStatus S = MCDisassembler::Success; 6118 6119 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6120 Inst.addOperand(MCOperand::createReg(0)); 6121 if (Inst.getOpcode() == ARM::VSCCLRMD) { 6122 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 6123 (fieldFromInstruction(Insn, 12, 4) << 8) | 6124 (fieldFromInstruction(Insn, 22, 1) << 12); 6125 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6126 return MCDisassembler::Fail; 6127 } 6128 } else { 6129 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 6130 (fieldFromInstruction(Insn, 22, 1) << 8) | 6131 (fieldFromInstruction(Insn, 12, 4) << 9); 6132 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 6133 return MCDisassembler::Fail; 6134 } 6135 } 6136 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6137 6138 return S; 6139 } 6140 6141 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6142 uint64_t Address, 6143 const void *Decoder) { 6144 if (RegNo > 7) 6145 return MCDisassembler::Fail; 6146 6147 unsigned Register = QPRDecoderTable[RegNo]; 6148 Inst.addOperand(MCOperand::createReg(Register)); 6149 return MCDisassembler::Success; 6150 } 6151 6152 static const uint16_t QQPRDecoderTable[] = { 6153 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6154 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6155 }; 6156 6157 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6158 uint64_t Address, 6159 const void *Decoder) { 6160 if (RegNo > 6) 6161 return MCDisassembler::Fail; 6162 6163 unsigned Register = QQPRDecoderTable[RegNo]; 6164 Inst.addOperand(MCOperand::createReg(Register)); 6165 return MCDisassembler::Success; 6166 } 6167 6168 static const uint16_t QQQQPRDecoderTable[] = { 6169 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6170 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6171 }; 6172 6173 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6174 uint64_t Address, 6175 const void *Decoder) { 6176 if (RegNo > 4) 6177 return MCDisassembler::Fail; 6178 6179 unsigned Register = QQQQPRDecoderTable[RegNo]; 6180 Inst.addOperand(MCOperand::createReg(Register)); 6181 return MCDisassembler::Success; 6182 } 6183 6184 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6185 uint64_t Address, 6186 const void *Decoder) { 6187 DecodeStatus S = MCDisassembler::Success; 6188 6189 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6190 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6191 // 't' as 0 and finish with a 1. 6192 unsigned Imm = 0; 6193 // We always start with a 't'. 6194 unsigned CurBit = 0; 6195 for (int i = 3; i >= 0; --i) { 6196 // If the bit we are looking at is not the same as last one, invert the 6197 // CurBit, if it is the same leave it as is. 6198 CurBit ^= (Val >> i) & 1U; 6199 6200 // Encode the CurBit at the right place in the immediate. 6201 Imm |= (CurBit << i); 6202 6203 // If we are done, finish the encoding with a 1. 6204 if ((Val & ~(~0U << i)) == 0) { 6205 Imm |= 1U << i; 6206 break; 6207 } 6208 } 6209 6210 Inst.addOperand(MCOperand::createImm(Imm)); 6211 6212 return S; 6213 } 6214 6215 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6216 uint64_t Address, const void *Decoder) { 6217 // The vpred_r operand type includes an MQPR register field derived 6218 // from the encoding. But we don't actually want to add an operand 6219 // to the MCInst at this stage, because AddThumbPredicate will do it 6220 // later, and will infer the register number from the TIED_TO 6221 // constraint. So this is a deliberately empty decoder method that 6222 // will inhibit the auto-generated disassembly code from adding an 6223 // operand at all. 6224 return MCDisassembler::Success; 6225 } 6226 6227 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 6228 unsigned Val, 6229 uint64_t Address, 6230 const void *Decoder) { 6231 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6232 return MCDisassembler::Success; 6233 } 6234 6235 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 6236 unsigned Val, 6237 uint64_t Address, 6238 const void *Decoder) { 6239 unsigned Code; 6240 switch (Val & 0x3) { 6241 case 0: 6242 Code = ARMCC::GE; 6243 break; 6244 case 1: 6245 Code = ARMCC::LT; 6246 break; 6247 case 2: 6248 Code = ARMCC::GT; 6249 break; 6250 case 3: 6251 Code = ARMCC::LE; 6252 break; 6253 } 6254 Inst.addOperand(MCOperand::createImm(Code)); 6255 return MCDisassembler::Success; 6256 } 6257 6258 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 6259 unsigned Val, 6260 uint64_t Address, 6261 const void *Decoder) { 6262 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6263 return MCDisassembler::Success; 6264 } 6265 6266 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 6267 uint64_t Address, 6268 const void *Decoder) { 6269 unsigned Code; 6270 switch (Val) { 6271 default: 6272 return MCDisassembler::Fail; 6273 case 0: 6274 Code = ARMCC::EQ; 6275 break; 6276 case 1: 6277 Code = ARMCC::NE; 6278 break; 6279 case 4: 6280 Code = ARMCC::GE; 6281 break; 6282 case 5: 6283 Code = ARMCC::LT; 6284 break; 6285 case 6: 6286 Code = ARMCC::GT; 6287 break; 6288 case 7: 6289 Code = ARMCC::LE; 6290 break; 6291 } 6292 6293 Inst.addOperand(MCOperand::createImm(Code)); 6294 return MCDisassembler::Success; 6295 } 6296 6297 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6298 uint64_t Address, const void *Decoder) { 6299 DecodeStatus S = MCDisassembler::Success; 6300 6301 unsigned DecodedVal = 64 - Val; 6302 6303 switch (Inst.getOpcode()) { 6304 case ARM::MVE_VCVTf16s16_fix: 6305 case ARM::MVE_VCVTs16f16_fix: 6306 case ARM::MVE_VCVTf16u16_fix: 6307 case ARM::MVE_VCVTu16f16_fix: 6308 if (DecodedVal > 16) 6309 return MCDisassembler::Fail; 6310 break; 6311 case ARM::MVE_VCVTf32s32_fix: 6312 case ARM::MVE_VCVTs32f32_fix: 6313 case ARM::MVE_VCVTf32u32_fix: 6314 case ARM::MVE_VCVTu32f32_fix: 6315 if (DecodedVal > 32) 6316 return MCDisassembler::Fail; 6317 break; 6318 } 6319 6320 Inst.addOperand(MCOperand::createImm(64 - Val)); 6321 6322 return S; 6323 } 6324 6325 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6326 switch (Opcode) { 6327 case ARM::VSTR_P0_off: 6328 case ARM::VSTR_P0_pre: 6329 case ARM::VSTR_P0_post: 6330 case ARM::VLDR_P0_off: 6331 case ARM::VLDR_P0_pre: 6332 case ARM::VLDR_P0_post: 6333 return ARM::P0; 6334 default: 6335 return 0; 6336 } 6337 } 6338 6339 template<bool Writeback> 6340 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6341 uint64_t Address, 6342 const void *Decoder) { 6343 switch (Inst.getOpcode()) { 6344 case ARM::VSTR_FPSCR_pre: 6345 case ARM::VSTR_FPSCR_NZCVQC_pre: 6346 case ARM::VLDR_FPSCR_pre: 6347 case ARM::VLDR_FPSCR_NZCVQC_pre: 6348 case ARM::VSTR_FPSCR_off: 6349 case ARM::VSTR_FPSCR_NZCVQC_off: 6350 case ARM::VLDR_FPSCR_off: 6351 case ARM::VLDR_FPSCR_NZCVQC_off: 6352 case ARM::VSTR_FPSCR_post: 6353 case ARM::VSTR_FPSCR_NZCVQC_post: 6354 case ARM::VLDR_FPSCR_post: 6355 case ARM::VLDR_FPSCR_NZCVQC_post: 6356 const FeatureBitset &featureBits = 6357 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6358 6359 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6360 return MCDisassembler::Fail; 6361 } 6362 6363 DecodeStatus S = MCDisassembler::Success; 6364 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6365 Inst.addOperand(MCOperand::createReg(Sysreg)); 6366 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6367 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6368 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6369 6370 if (Writeback) { 6371 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6372 return MCDisassembler::Fail; 6373 } 6374 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6375 return MCDisassembler::Fail; 6376 6377 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6378 Inst.addOperand(MCOperand::createReg(0)); 6379 6380 return S; 6381 } 6382 6383 static inline DecodeStatus DecodeMVE_MEM_pre( 6384 MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder, 6385 unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6386 DecodeStatus S = MCDisassembler::Success; 6387 6388 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6389 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6390 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6391 6392 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6393 return MCDisassembler::Fail; 6394 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6395 return MCDisassembler::Fail; 6396 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6397 return MCDisassembler::Fail; 6398 6399 return S; 6400 } 6401 6402 template <int shift> 6403 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6404 uint64_t Address, const void *Decoder) { 6405 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6406 fieldFromInstruction(Val, 16, 3), 6407 DecodetGPRRegisterClass, 6408 DecodeTAddrModeImm7<shift>); 6409 } 6410 6411 template <int shift> 6412 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6413 uint64_t Address, const void *Decoder) { 6414 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6415 fieldFromInstruction(Val, 16, 4), 6416 DecoderGPRRegisterClass, 6417 DecodeT2AddrModeImm7<shift,1>); 6418 } 6419 6420 template <int shift> 6421 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6422 uint64_t Address, const void *Decoder) { 6423 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6424 fieldFromInstruction(Val, 17, 3), 6425 DecodeMQPRRegisterClass, 6426 DecodeMveAddrModeQ<shift>); 6427 } 6428 6429 template<unsigned MinLog, unsigned MaxLog> 6430 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6431 uint64_t Address, 6432 const void *Decoder) { 6433 DecodeStatus S = MCDisassembler::Success; 6434 6435 if (Val < MinLog || Val > MaxLog) 6436 return MCDisassembler::Fail; 6437 6438 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6439 return S; 6440 } 6441 6442 template<unsigned start> 6443 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 6444 uint64_t Address, 6445 const void *Decoder) { 6446 DecodeStatus S = MCDisassembler::Success; 6447 6448 Inst.addOperand(MCOperand::createImm(start + Val)); 6449 6450 return S; 6451 } 6452 6453 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6454 uint64_t Address, const void *Decoder) { 6455 DecodeStatus S = MCDisassembler::Success; 6456 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6457 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6458 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6459 fieldFromInstruction(Insn, 13, 3)); 6460 unsigned index = fieldFromInstruction(Insn, 4, 1); 6461 6462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6463 return MCDisassembler::Fail; 6464 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6465 return MCDisassembler::Fail; 6466 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6467 return MCDisassembler::Fail; 6468 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6469 return MCDisassembler::Fail; 6470 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6471 return MCDisassembler::Fail; 6472 6473 return S; 6474 } 6475 6476 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6477 uint64_t Address, const void *Decoder) { 6478 DecodeStatus S = MCDisassembler::Success; 6479 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6480 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6481 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6482 fieldFromInstruction(Insn, 13, 3)); 6483 unsigned index = fieldFromInstruction(Insn, 4, 1); 6484 6485 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6486 return MCDisassembler::Fail; 6487 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6488 return MCDisassembler::Fail; 6489 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6490 return MCDisassembler::Fail; 6491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6492 return MCDisassembler::Fail; 6493 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6494 return MCDisassembler::Fail; 6495 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6496 return MCDisassembler::Fail; 6497 6498 return S; 6499 } 6500 6501 static DecodeStatus DecodeMVEOverlappingLongShift( 6502 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6503 DecodeStatus S = MCDisassembler::Success; 6504 6505 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6506 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6507 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6508 6509 if (RdaHi == 14) { 6510 // This value of RdaHi (really indicating pc, because RdaHi has to 6511 // be an odd-numbered register, so the low bit will be set by the 6512 // decode function below) indicates that we must decode as SQRSHR 6513 // or UQRSHL, which both have a single Rda register field with all 6514 // four bits. 6515 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6516 6517 switch (Inst.getOpcode()) { 6518 case ARM::MVE_ASRLr: 6519 case ARM::MVE_SQRSHRL: 6520 Inst.setOpcode(ARM::MVE_SQRSHR); 6521 break; 6522 case ARM::MVE_LSLLr: 6523 case ARM::MVE_UQRSHLL: 6524 Inst.setOpcode(ARM::MVE_UQRSHL); 6525 break; 6526 default: 6527 llvm_unreachable("Unexpected starting opcode!"); 6528 } 6529 6530 // Rda as output parameter 6531 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6532 return MCDisassembler::Fail; 6533 6534 // Rda again as input parameter 6535 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6536 return MCDisassembler::Fail; 6537 6538 // Rm, the amount to shift by 6539 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6540 return MCDisassembler::Fail; 6541 6542 if (fieldFromInstruction (Insn, 6, 3) != 4) 6543 return MCDisassembler::SoftFail; 6544 6545 if (Rda == Rm) 6546 return MCDisassembler::SoftFail; 6547 6548 return S; 6549 } 6550 6551 // Otherwise, we decode as whichever opcode our caller has already 6552 // put into Inst. Those all look the same: 6553 6554 // RdaLo,RdaHi as output parameters 6555 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6556 return MCDisassembler::Fail; 6557 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6558 return MCDisassembler::Fail; 6559 6560 // RdaLo,RdaHi again as input parameters 6561 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6562 return MCDisassembler::Fail; 6563 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6564 return MCDisassembler::Fail; 6565 6566 // Rm, the amount to shift by 6567 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6568 return MCDisassembler::Fail; 6569 6570 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || 6571 Inst.getOpcode() == ARM::MVE_UQRSHLL) { 6572 unsigned Saturate = fieldFromInstruction(Insn, 7, 1); 6573 // Saturate, the bit position for saturation 6574 Inst.addOperand(MCOperand::createImm(Saturate)); 6575 } 6576 6577 return S; 6578 } 6579 6580 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, 6581 const void *Decoder) { 6582 DecodeStatus S = MCDisassembler::Success; 6583 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6584 fieldFromInstruction(Insn, 13, 3)); 6585 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6586 fieldFromInstruction(Insn, 1, 3)); 6587 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6588 6589 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6590 return MCDisassembler::Fail; 6591 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6592 return MCDisassembler::Fail; 6593 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6594 return MCDisassembler::Fail; 6595 6596 return S; 6597 } 6598 6599 template<bool scalar, OperandDecoder predicate_decoder> 6600 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6601 const void *Decoder) { 6602 DecodeStatus S = MCDisassembler::Success; 6603 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6604 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6605 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6606 return MCDisassembler::Fail; 6607 6608 unsigned fc; 6609 6610 if (scalar) { 6611 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6612 fieldFromInstruction(Insn, 7, 1) | 6613 fieldFromInstruction(Insn, 5, 1) << 1; 6614 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6615 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6616 return MCDisassembler::Fail; 6617 } else { 6618 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6619 fieldFromInstruction(Insn, 7, 1) | 6620 fieldFromInstruction(Insn, 0, 1) << 1; 6621 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6622 fieldFromInstruction(Insn, 1, 3); 6623 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6624 return MCDisassembler::Fail; 6625 } 6626 6627 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6628 return MCDisassembler::Fail; 6629 6630 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6631 Inst.addOperand(MCOperand::createReg(0)); 6632 Inst.addOperand(MCOperand::createImm(0)); 6633 6634 return S; 6635 } 6636 6637 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6638 const void *Decoder) { 6639 DecodeStatus S = MCDisassembler::Success; 6640 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6641 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6642 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6643 return MCDisassembler::Fail; 6644 return S; 6645 } 6646 6647 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, 6648 const void *Decoder) { 6649 DecodeStatus S = MCDisassembler::Success; 6650 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6651 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6652 return S; 6653 } 6654 6655 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 6656 uint64_t Address, const void *Decoder) { 6657 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 6658 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6659 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 | 6660 fieldFromInstruction(Insn, 12, 3) << 8 | 6661 fieldFromInstruction(Insn, 0, 8); 6662 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1); 6663 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 6664 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 6665 unsigned S = fieldFromInstruction(Insn, 20, 1); 6666 if (sign1 != sign2) 6667 return MCDisassembler::Fail; 6668 6669 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) 6670 DecodeStatus DS = MCDisassembler::Success; 6671 if ((!Check(DS, 6672 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst 6673 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) 6674 return MCDisassembler::Fail; 6675 if (TypeT3) { 6676 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); 6677 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12 6678 } else { 6679 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); 6680 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 6681 return MCDisassembler::Fail; 6682 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out 6683 return MCDisassembler::Fail; 6684 } 6685 6686 return DS; 6687 } 6688
Indexes created Wed Jun 10 00:26:05 UTC 2026